# Library script # # Exported from c:/olin/eagle/lib/pic.lbr at 2005-04-29 16:10:13 # # EAGLE Version 4.14 Copyright (c) 1988-2005 CadSoft # Set Wire_Bend 2; # Grid changed to 'mm' to avoid loss of precision! Grid mm; Layer 1 Top; Layer 2 Route2; Layer 15 Route15; Layer 16 Bottom; Layer 17 Pads; Layer 18 Vias; Layer 19 Unrouted; Layer 20 Dimension; Layer 21 tPlace; Layer 22 bPlace; Layer 23 tOrigins; Layer 24 bOrigins; Layer 25 tNames; Layer 26 bNames; Layer 27 tValues; Layer 28 bValues; Layer 29 tStop; Layer 30 bStop; Layer 31 tCream; Layer 32 bCream; Layer 33 tFinish; Layer 34 bFinish; Layer 35 tGlue; Layer 36 bGlue; Layer 37 tTest; Layer 38 bTest; Layer 39 tKeepout; Layer 40 bKeepout; Layer 41 tRestrict; Layer 42 bRestrict; Layer 43 vRestrict; Layer 44 Drills; Layer 45 Holes; Layer 46 Milling; Layer 47 Measures; Layer 48 Document; Layer 49 Reference; Layer 51 tDocu; Layer 52 bDocu; Layer 91 Nets; Layer 92 Busses; Layer 93 Pins; Layer 94 Symbols; Layer 95 Names; Layer 96 Values; Description 'Microchip PIC microcontrollers'; Edit 16F876.sym; Layer 94; Change Style Continuous; Wire 0.254 (-20.32 30.48) (20.32 30.48) (20.32 -30.48) (-20.32 -30.48) \ (-20.32 30.48); Pin 'VSS1' Pwr None Middle R90 Both 1 (-2.54 -35.56); Pin 'VSS2' Pwr None Middle R90 Both 1 (2.54 -35.56); Pin 'MCLR-' In None Middle R0 Both 0 (-25.4 20.32); Pin 'OSC1/CLKIN' In None Middle R0 Both 0 (-25.4 15.24); Pin 'OSC2/CLKOUT' Out None Middle R0 Both 0 (-25.4 12.7); Pin 'RB0/INT' I/O None Middle R180 Both 0 (25.4 20.32); Pin 'RB1' I/O None Middle R180 Both 0 (25.4 17.78); Pin 'RB2' I/O None Middle R180 Both 0 (25.4 15.24); Pin 'RB3/LVPGM' I/O None Middle R180 Both 0 (25.4 12.7); Pin 'RB4' I/O None Middle R180 Both 0 (25.4 10.16); Pin 'RB5' I/O None Middle R180 Both 0 (25.4 7.62); Pin 'RB6/PGC' I/O None Middle R180 Both 0 (25.4 5.08); Pin 'RB7/PGD' I/O None Middle R180 Both 0 (25.4 2.54); Pin 'RC0/T1OSO/T1CKIN' I/O None Middle R180 Both 0 (25.4 -2.54); Pin 'RC1/T1OSI/CCP2' I/O None Middle R180 Both 0 (25.4 -5.08); Pin 'RC2/CCP1' I/O None Middle R180 Both 0 (25.4 -7.62); Pin 'RC3/SCK/SCL' I/O None Middle R180 Both 0 (25.4 -10.16); Pin 'RC4/SDI/SDA' I/O None Middle R180 Both 0 (25.4 -12.7); Pin 'RC5/SD0' I/O None Middle R180 Both 0 (25.4 -15.24); Pin 'RC6/TX/CK' I/O None Middle R180 Both 0 (25.4 -17.78); Pin 'RC7/RX/DT' I/O None Middle R180 Both 0 (25.4 -20.32); Pin 'RA0/AN0' I/O None Middle R0 Both 0 (-25.4 -2.54); Pin 'RA1/AN1' I/O None Middle R0 Both 0 (-25.4 -5.08); Pin 'RA2/AN2/VREF-' I/O None Middle R0 Both 0 (-25.4 -7.62); Pin 'RA3/AN3/VREF+' I/O None Middle R0 Both 0 (-25.4 -10.16); Pin 'RA4/T0CKIN' OC None Middle R0 Both 0 (-25.4 -12.7); Pin 'RA5/AN4/SS-' I/O None Middle R0 Both 0 (-25.4 -15.24); Pin 'VDD' Pwr None Middle R270 Both 0 (0 35.56); Layer 96; Change Size 1.778; Change Ratio 8; Change Font Proportional; Text '>value' R0 (-17.78 5.08); Layer 95; Change Size 1.905; Change Ratio 8; Text '>NAME' R0 (3.81 31.115); Edit 16C773.sym; Layer 94; Wire 0.254 (-20.32 30.48) (20.32 30.48) (20.32 -30.48) (-20.32 -30.48) \ (-20.32 30.48); Pin 'AVSS' Pwr None Middle R90 Both 0 (-2.54 -35.56); Pin 'VSS' Pwr None Middle R90 Both 0 (2.54 -35.56); Pin 'MCLR-' In None Middle R0 Both 0 (-25.4 20.32); Pin 'OSC1/CLKIN' In None Middle R0 Both 0 (-25.4 15.24); Pin 'OSC2/CLKOUT' Out None Middle R0 Both 0 (-25.4 12.7); Pin 'RB0/INT' I/O None Middle R180 Both 0 (25.4 20.32); Pin 'RB1/SS-' I/O None Middle R180 Both 0 (25.4 17.78); Pin 'RB2/AN8' I/O None Middle R180 Both 0 (25.4 15.24); Pin 'RB3/AN9/LVPGM' I/O None Middle R180 Both 0 (25.4 12.7); Pin 'RB4' I/O None Middle R180 Both 0 (25.4 10.16); Pin 'RB5' I/O None Middle R180 Both 0 (25.4 7.62); Pin 'RB6/PGC' I/O None Middle R180 Both 0 (25.4 5.08); Pin 'RB7/PGD' I/O None Middle R180 Both 0 (25.4 2.54); Pin 'RC0/T1OSO/T1CKIN' I/O None Middle R180 Both 0 (25.4 -2.54); Pin 'RC1/T1OSI/CCP2' I/O None Middle R180 Both 0 (25.4 -5.08); Pin 'RC2/CCP1' I/O None Middle R180 Both 0 (25.4 -7.62); Pin 'RC3/SCK/SCL' I/O None Middle R180 Both 0 (25.4 -10.16); Pin 'RC4/SDI/SDA' I/O None Middle R180 Both 0 (25.4 -12.7); Pin 'RC5/SD0' I/O None Middle R180 Both 0 (25.4 -15.24); Pin 'RC6/TX/CK' I/O None Middle R180 Both 0 (25.4 -17.78); Pin 'RC7/RX/DT' I/O None Middle R180 Both 0 (25.4 -20.32); Pin 'RA0/AN0' I/O None Middle R0 Both 0 (-25.4 -2.54); Pin 'RA1/AN1' I/O None Middle R0 Both 0 (-25.4 -5.08); Pin 'RA2/AN2/VREF-' I/O None Middle R0 Both 0 (-25.4 -7.62); Pin 'RA3/AN3/VREF+' I/O None Middle R0 Both 0 (-25.4 -10.16); Pin 'RA4/T0CKIN' I/O None Middle R0 Both 0 (-25.4 -12.7); Pin 'AVDD' Pwr None Middle R270 Both 0 (-2.54 35.56); Layer 96; Change Size 1.778; Change Ratio 8; Text '>value' R0 (-17.78 5.08); Pin 'VDD' Pwr None Middle R270 Both 0 (2.54 35.56); Layer 95; Change Size 1.905; Change Ratio 8; Text '>NAME' R0 (5.715 31.115); Edit 16F877.sym; Layer 94; Wire 0.254 (-20.32 40.64) (20.32 40.64) (20.32 -38.1) (-20.32 -38.1) \ (-20.32 40.64); Pin 'VSS1' Pwr None Middle R90 Both 2 (-2.54 -43.18); Pin 'VSS2' Pwr None Middle R90 Both 2 (2.54 -43.18); Pin 'MCLR-' In None Middle R0 Both 0 (-25.4 33.02); Pin 'OSC1/CLKIN' In None Middle R0 Both 0 (-25.4 27.94); Pin 'OSC2/CLKOUT' Out None Middle R0 Both 0 (-25.4 25.4); Pin 'RB0/INT' I/O None Middle R180 Both 0 (25.4 33.02); Pin 'RB1' I/O None Middle R180 Both 0 (25.4 30.48); Pin 'RB2' I/O None Middle R180 Both 0 (25.4 27.94); Pin 'RB3/LVPGM' I/O None Middle R180 Both 0 (25.4 25.4); Pin 'RB4' I/O None Middle R180 Both 0 (25.4 22.86); Pin 'RB5' I/O None Middle R180 Both 0 (25.4 20.32); Pin 'RB6/PGC' I/O None Middle R180 Both 0 (25.4 17.78); Pin 'RB7/PGD' I/O None Middle R180 Both 0 (25.4 15.24); Pin 'RC0/T1OSO/T1CKIN' I/O None Middle R180 Both 0 (25.4 10.16); Pin 'RC1/T1OSI/CCP2' I/O None Middle R180 Both 0 (25.4 7.62); Pin 'RC2/CCP1' I/O None Middle R180 Both 0 (25.4 5.08); Pin 'RC3/SCK/SCL' I/O None Middle R180 Both 0 (25.4 2.54); Pin 'RC4/SDI/SDA' I/O None Middle R180 Both 0 (25.4 0); Pin 'RC5/SD0' I/O None Middle R180 Both 0 (25.4 -2.54); Pin 'RC6/TX/CK' I/O None Middle R180 Both 0 (25.4 -5.08); Pin 'RC7/RX/DT' I/O None Middle R180 Both 0 (25.4 -7.62); Pin 'RA0/AN0' I/O None Middle R0 Both 0 (-25.4 10.16); Pin 'RA1/AN1' I/O None Middle R0 Both 0 (-25.4 7.62); Pin 'RA2/AN2/VREF-' I/O None Middle R0 Both 0 (-25.4 5.08); Pin 'RA3/AN3/VREF+' I/O None Middle R0 Both 0 (-25.4 2.54); Pin 'RA4/T0CKIN' OC None Middle R0 Both 0 (-25.4 0); Pin 'RA5/AN4/SS-' I/O None Middle R0 Both 0 (-25.4 -2.54); Pin 'VDD1' Pwr None Middle R270 Both 1 (-2.54 45.72); Layer 96; Change Size 1.778; Change Ratio 8; Text '>value' R0 (-17.78 17.78); Layer 95; Change Size 1.905; Change Ratio 8; Text '>NAME' R0 (6.35 41.275); Pin 'RD0' I/O None Middle R180 Both 0 (25.4 -12.7); Pin 'RD1' I/O None Middle R180 Both 0 (25.4 -15.24); Pin 'RD2' I/O None Middle R180 Both 0 (25.4 -17.78); Pin 'RD3' I/O None Middle R180 Both 0 (25.4 -20.32); Pin 'RD4' I/O None Middle R180 Both 0 (25.4 -22.86); Pin 'RD5' I/O None Middle R180 Both 0 (25.4 -25.4); Pin 'RD6' I/O None Middle R180 Both 0 (25.4 -27.94); Pin 'RD7' I/O None Middle R180 Both 0 (25.4 -30.48); Pin 'RE0/RD/AN5' I/O None Middle R0 Both 0 (-25.4 -12.7); Pin 'RE1/WR/AN6' I/O None Middle R0 Both 0 (-25.4 -15.24); Pin 'RE2/CS/AN7' I/O None Middle R0 Both 0 (-25.4 -17.78); Pin 'VDD2' Pwr None Middle R270 Both 1 (2.54 45.72); Edit 16C622.sym; Layer 94; Wire 0.254 (-20.32 30.48) (20.32 30.48) (20.32 -17.78) (-20.32 -17.78) \ (-20.32 30.48); Pin 'VSS' Pwr None Middle R90 Both 1 (0 -22.86); Pin 'MCLR-' In None Middle R0 Both 0 (-25.4 20.32); Pin 'OSC1/CLKIN' In None Middle R0 Both 0 (-25.4 15.24); Pin 'OSC2/CLKOUT' Out None Middle R0 Both 0 (-25.4 12.7); Pin 'RB0/INT' I/O None Middle R180 Both 0 (25.4 20.32); Pin 'RB1' I/O None Middle R180 Both 0 (25.4 17.78); Pin 'RB2' I/O None Middle R180 Both 0 (25.4 15.24); Pin 'RB3' I/O None Middle R180 Both 0 (25.4 12.7); Pin 'RB4' I/O None Middle R180 Both 0 (25.4 10.16); Pin 'RB5' I/O None Middle R180 Both 0 (25.4 7.62); Pin 'RB6' I/O None Middle R180 Both 0 (25.4 5.08); Pin 'RB7' I/O None Middle R180 Both 0 (25.4 2.54); Pin 'RA0/AN0' I/O None Middle R0 Both 0 (-25.4 5.08); Pin 'RA1/AN1' I/O None Middle R0 Both 0 (-25.4 2.54); Pin 'RA2/AN2/VREF' I/O None Middle R0 Both 0 (-25.4 0); Pin 'RA3/AN3' I/O None Middle R0 Both 0 (-25.4 -2.54); Pin 'RA4/T0CKIN' I/O None Middle R0 Both 0 (-25.4 -5.08); Pin 'VDD' Pwr None Middle R270 Both 0 (0 35.56); Layer 96; Change Size 1.778; Change Ratio 8; Text '>value' R0 (1.905 31.115); Layer 95; Change Size 1.905; Change Ratio 8; Text '>NAME' R0 (-19.05 31.115); Edit 16F628.sym; Layer 94; Wire 0.254 (-25.4 20.32) (25.4 20.32) (25.4 -17.78) (-25.4 -17.78) \ (-25.4 20.32); Pin 'VSS' Pwr None Middle R90 Both 0 (0 -22.86); Pin 'RB0/INT' I/O None Middle R180 Both 0 (30.48 10.16); Pin 'RB1/RX/DT' I/O None Middle R180 Both 0 (30.48 7.62); Pin 'RB2/TX/CK' I/O None Middle R180 Both 0 (30.48 5.08); Pin 'RB3/CCP1' I/O None Middle R180 Both 0 (30.48 2.54); Pin 'RB4/PGM' I/O None Middle R180 Both 0 (30.48 0); Pin 'RB5' I/O None Middle R180 Both 0 (30.48 -2.54); Pin 'RB6/T1OSO/T1CLK' I/O None Middle R180 Both 0 (30.48 -5.08); Pin 'RB7/T1OSI' I/O None Middle R180 Both 0 (30.48 -7.62); Pin 'RA0/AN0' I/O None Middle R0 Both 0 (-30.48 10.16); Pin 'RA1/AN1' I/O None Middle R0 Both 0 (-30.48 7.62); Pin 'RA2/AN2/VREF' I/O None Middle R0 Both 0 (-30.48 5.08); Pin 'RA3/AN3/CMP1' I/O None Middle R0 Both 0 (-30.48 2.54); Pin 'RA4/T0CKIN/CMP2' In None Middle R0 Both 0 (-30.48 0); Pin 'VDD' Pwr None Middle R270 Both 0 (0 25.4); Layer 96; Change Size 1.778; Change Ratio 8; Text '>value' R0 (-24.765 17.78); Layer 95; Change Size 1.905; Change Ratio 8; Text '>NAME' R0 (-24.765 20.955); Pin 'RA5/MCLR/THV' I/O None Middle R0 Both 0 (-30.48 -2.54); Pin 'RA6/OSC2/CLKOUT' I/O None Middle R0 Both 0 (-30.48 -5.08); Pin 'RA7/OSC1/CLKIN' I/O None Middle R0 Both 0 (-30.48 -7.62); Edit 12F675.sym; Layer 94; Wire 0.254 (-17.78 15.24) (15.24 15.24) (15.24 -17.78) (-17.78 -17.78) \ (-17.78 15.24); Pin 'VSS' Pwr None Middle R90 Both 0 (0 -22.86); Pin 'VDD' Pwr None Middle R270 Both 0 (0 20.32); Layer 96; Change Size 1.778; Change Ratio 8; Text '>value' R0 (-17.145 12.7); Layer 95; Change Size 1.905; Change Ratio 8; Text '>NAME' R0 (-17.145 15.875); Pin 'GP3/MCLR' In None Middle R0 Both 0 (-22.86 -2.54); Pin 'GP0/AN0/CIN+' I/O None Middle R0 Both 0 (-22.86 5.08); Pin 'GP1/AN1/CIN-' I/O None Middle R0 Both 0 (-22.86 2.54); Pin 'GP2/AN2/T0CKI/INT/COUT' I/O None Middle R0 Both 0 (-22.86 0); Pin 'GP4/T1G/OSC2/CLKOUT' I/O None Middle R0 Both 0 (-22.86 -5.08); Pin 'GP5/T1CKI/OSC1/CLKIN' I/O None Middle R0 Both 0 (-22.86 -7.62); Edit 12F629.sym; Layer 94; Wire 0.254 (-17.78 15.24) (15.24 15.24) (15.24 -17.78) (-17.78 -17.78) \ (-17.78 15.24); Pin 'VSS' Pwr None Middle R90 Both 0 (0 -22.86); Pin 'VDD' Pwr None Middle R270 Both 0 (0 20.32); Layer 96; Change Size 1.778; Change Ratio 8; Text '>value' R0 (-17.145 12.7); Layer 95; Change Size 1.905; Change Ratio 8; Text '>NAME' R0 (-17.145 15.875); Pin 'GP3/MCLR' In None Middle R0 Both 0 (-22.86 -2.54); Pin 'GP0/CIN+' I/O None Middle R0 Both 0 (-22.86 5.08); Pin 'GP1/CIN-' I/O None Middle R0 Both 0 (-22.86 2.54); Pin 'GP2/T0CKI/INT/COUT' I/O None Middle R0 Both 0 (-22.86 0); Pin 'GP4/T1G/OSC2/CLKOUT' I/O None Middle R0 Both 0 (-22.86 -5.08); Pin 'GP5/T1CKI/OSC1/CLKIN' I/O None Middle R0 Both 0 (-22.86 -7.62); Edit 18F4X2.sym; Layer 94; Wire 0.254 (-20.32 40.64) (20.32 40.64) (20.32 -38.1) (-20.32 -38.1) \ (-20.32 40.64); Pin 'VSS1' Pwr None Middle R90 Both 2 (-2.54 -43.18); Pin 'VSS2' Pwr None Middle R90 Both 2 (2.54 -43.18); Pin 'MCLR/VPP' In None Middle R0 Both 0 (-25.4 33.02); Pin 'OSC1/CKIN' In None Middle R0 Both 0 (-25.4 27.94); Pin 'OSC2/CKOUT/RA6' Out None Middle R0 Both 0 (-25.4 25.4); Pin 'RB0/INT0' I/O None Middle R180 Both 0 (25.4 33.02); Pin 'RB1/INT1' I/O None Middle R180 Both 0 (25.4 30.48); Pin 'RB2/INT2' I/O None Middle R180 Both 0 (25.4 27.94); Pin 'RB3/CCP2' I/O None Middle R180 Both 0 (25.4 25.4); Pin 'RB4' I/O None Middle R180 Both 0 (25.4 22.86); Pin 'RB5/PGM' I/O None Middle R180 Both 0 (25.4 20.32); Pin 'RB6/PGC' I/O None Middle R180 Both 0 (25.4 17.78); Pin 'RB7/PGD' I/O None Middle R180 Both 0 (25.4 15.24); Pin 'RC0/T1OSO/T1CKIN' I/O None Middle R180 Both 0 (25.4 10.16); Pin 'RC1/T1OSI/CCP2' I/O None Middle R180 Both 0 (25.4 7.62); Pin 'RC2/CCP1' I/O None Middle R180 Both 0 (25.4 5.08); Pin 'RC3/SCK/SCL' I/O None Middle R180 Both 0 (25.4 2.54); Pin 'RC4/SDI/SDA' I/O None Middle R180 Both 0 (25.4 0); Pin 'RC5/SDO' I/O None Middle R180 Both 0 (25.4 -2.54); Pin 'RC6/TX/UCK' I/O None Middle R180 Both 0 (25.4 -5.08); Pin 'RC7/RX/UDT' I/O None Middle R180 Both 0 (25.4 -7.62); Pin 'RA0/AN0' I/O None Middle R0 Both 0 (-25.4 10.16); Pin 'RA1/AN1' I/O None Middle R0 Both 0 (-25.4 7.62); Pin 'RA2/AN2/VREF-' I/O None Middle R0 Both 0 (-25.4 5.08); Pin 'RA3/AN3/VREF+' I/O None Middle R0 Both 0 (-25.4 2.54); Pin 'RA4/T0CKIN' OC None Middle R0 Both 0 (-25.4 0); Pin 'RA5/AN4/SS/LVIN' I/O None Middle R0 Both 0 (-25.4 -2.54); Pin 'VDD1' Pwr None Middle R270 Both 1 (-2.54 45.72); Layer 96; Change Size 1.778; Change Ratio 8; Text '>value' R0 (-17.78 17.78); Layer 95; Change Size 1.905; Change Ratio 8; Text '>NAME' R0 (6.35 41.275); Pin 'RD0' I/O None Middle R180 Both 0 (25.4 -12.7); Pin 'RD1' I/O None Middle R180 Both 0 (25.4 -15.24); Pin 'RD2' I/O None Middle R180 Both 0 (25.4 -17.78); Pin 'RD3' I/O None Middle R180 Both 0 (25.4 -20.32); Pin 'RD4' I/O None Middle R180 Both 0 (25.4 -22.86); Pin 'RD5' I/O None Middle R180 Both 0 (25.4 -25.4); Pin 'RD6' I/O None Middle R180 Both 0 (25.4 -27.94); Pin 'RD7' I/O None Middle R180 Both 0 (25.4 -30.48); Pin 'RE0/RD/AN5' I/O None Middle R0 Both 0 (-25.4 -12.7); Pin 'RE1/WR/AN6' I/O None Middle R0 Both 0 (-25.4 -15.24); Pin 'RE2/CS/AN7' I/O None Middle R0 Both 0 (-25.4 -17.78); Pin 'VDD2' Pwr None Middle R270 Both 1 (2.54 45.72); Edit 18F1320.sym; Layer 94; Wire 0.254 (-25.4 20.32) (25.4 20.32) (25.4 -17.78) (-25.4 -17.78) \ (-25.4 20.32); Pin 'VSS' Pwr None Middle R90 Both 0 (0 -22.86); Pin 'RB0/AN4/INT0' I/O None Middle R180 Both 0 (30.48 10.16); Pin 'RB1/AN5/INT1/TX/CK' I/O None Middle R180 Both 0 (30.48 7.62); Pin 'RB2/INT2/PIB' I/O None Middle R180 Both 0 (30.48 5.08); Pin 'RB3/CCP1/PIA' I/O None Middle R180 Both 0 (30.48 2.54); Pin 'RB4/AN6/RX/DT' I/O None Middle R180 Both 0 (30.48 0); Pin 'RB5/LVPGM' I/O None Middle R180 Both 0 (30.48 -2.54); Pin 'RB6/P1C/T1OSO/PGC' I/O None Middle R180 Both 0 (30.48 -5.08); Pin 'RB7/P1D/T1OSI/PGD' I/O None Middle R180 Both 0 (30.48 -7.62); Pin 'RA0/AN0' I/O None Middle R0 Both 0 (-30.48 10.16); Pin 'RA1/AN1/LVDIN' I/O None Middle R0 Both 0 (-30.48 7.62); Pin 'RA2/AN2/VREF-' I/O None Middle R0 Both 0 (-30.48 5.08); Pin 'RA3/AN3/VREF+' I/O None Middle R0 Both 0 (-30.48 2.54); Pin 'RA4/T0CKIN' I/O None Middle R0 Both 0 (-30.48 0); Pin 'VDD' Pwr None Middle R270 Both 0 (0 25.4); Layer 95; Change Size 1.905; Change Ratio 8; Text '>NAME' R0 (-24.765 20.955); Pin 'RA5/MCLR/VPP' In None Middle R0 Both 0 (-30.48 -2.54); Pin 'RA6/OSC2/CKOUT' I/O None Middle R0 Both 0 (-30.48 -5.08); Pin 'RA7/OSC1/CKIN' I/O None Middle R0 Both 0 (-30.48 -7.62); Layer 96; Change Size 1.905; Change Ratio 8; Text '>VALUE' R0 (-24.765 17.78); Edit 18F252.sym; Layer 94; Wire 0.254 (-25.4 30.48) (25.4 30.48) (25.4 -30.48) (-25.4 -30.48) \ (-25.4 30.48); Pin 'VSS1' Pwr None Middle R90 Both 1 (-2.54 -35.56); Pin 'VSS2' Pwr None Middle R90 Both 1 (2.54 -35.56); Pin 'MCLR/VPP' In None Middle R0 Both 0 (-30.48 20.32); Pin 'OSC1/CLKIN' In None Middle R0 Both 0 (-30.48 15.24); Pin 'OSC2/CLKOUT/RA6' Out None Middle R0 Both 0 (-30.48 12.7); Pin 'RB0/INT0' I/O None Middle R180 Both 0 (30.48 20.32); Pin 'RB1/INT1' I/O None Middle R180 Both 0 (30.48 17.78); Pin 'RB2/INT2' I/O None Middle R180 Both 0 (30.48 15.24); Pin 'RB3/CCP2B' I/O None Middle R180 Both 0 (30.48 12.7); Pin 'RB4' I/O None Middle R180 Both 0 (30.48 10.16); Pin 'RB5/LVPGM' I/O None Middle R180 Both 0 (30.48 7.62); Pin 'RB6/PGC' I/O None Middle R180 Both 0 (30.48 5.08); Pin 'RB7/PGD' I/O None Middle R180 Both 0 (30.48 2.54); Pin 'RC0/T1OSO/T1CKIN' I/O None Middle R180 Both 0 (30.48 -2.54); Pin 'RC1/T1OSI/CCP2A' I/O None Middle R180 Both 0 (30.48 -5.08); Pin 'RC2/CCP1' I/O None Middle R180 Both 0 (30.48 -7.62); Pin 'RC3/SCK/SCL' I/O None Middle R180 Both 0 (30.48 -10.16); Pin 'RC4/SDI/SDA' I/O None Middle R180 Both 0 (30.48 -12.7); Pin 'RC5/SD0' I/O None Middle R180 Both 0 (30.48 -15.24); Pin 'RC6/TX/CK' I/O None Middle R180 Both 0 (30.48 -17.78); Pin 'RC7/RX/DT' I/O None Middle R180 Both 0 (30.48 -20.32); Pin 'RA0/AN0' I/O None Middle R0 Both 0 (-30.48 -2.54); Pin 'RA1/AN1' I/O None Middle R0 Both 0 (-30.48 -5.08); Pin 'RA2/AN2/VREF-' I/O None Middle R0 Both 0 (-30.48 -7.62); Pin 'RA3/AN3/VREF+' I/O None Middle R0 Both 0 (-30.48 -10.16); Pin 'RA4/T0CKIN' OC None Middle R0 Both 0 (-30.48 -12.7); Pin 'RA5/AN4/SS/LVDIN' I/O None Middle R0 Both 0 (-30.48 -15.24); Pin 'VDD' Pwr None Middle R270 Both 0 (0 35.56); Layer 95; Change Size 1.905; Change Ratio 8; Text '>NAME' R0 (5.08 31.115); Layer 96; Change Size 1.905; Change Ratio 8; Text '>VALUE' R0 (-24.765 27.94); Edit 16F630.sym; Layer 94; Wire 0.254 (-22.86 17.78) (22.86 17.78) (22.86 -15.24) (-22.86 -15.24) \ (-22.86 17.78); Pin 'VSS' Pwr None Middle R90 Both 0 (0 -20.32); Pin 'RC0' I/O None Middle R180 Both 0 (27.94 7.62); Pin 'RC1' I/O None Middle R180 Both 0 (27.94 5.08); Pin 'RC2' I/O None Middle R180 Both 0 (27.94 2.54); Pin 'RC3' I/O None Middle R180 Both 0 (27.94 0); Pin 'RC4' I/O None Middle R180 Both 0 (27.94 -2.54); Pin 'RC5' I/O None Middle R180 Both 0 (27.94 -5.08); Pin 'RA0/CIN+/PGD' I/O None Middle R0 Both 0 (-27.94 7.62); Pin 'RA1/CIN-/PGC' I/O None Middle R0 Both 0 (-27.94 5.08); Pin 'RA2/INT/COUT/T0CKIN' I/O None Middle R0 Both 0 (-27.94 2.54); Pin 'RA3/MCLR/VPP' In None Middle R0 Both 0 (-27.94 0); Pin 'RA4/T1GATE/OSCOUT' I/O None Middle R0 Both 0 (-27.94 -2.54); Pin 'VDD' Pwr None Middle R270 Both 0 (0 22.86); Layer 96; Change Size 1.778; Change Ratio 8; Text '>value' R0 (-22.225 15.24); Layer 95; Change Size 1.905; Change Ratio 8; Text '>NAME' R0 (-22.225 18.415); Pin 'RA5/T1CKIN/OSCIN' I/O None Middle R0 Both 0 (-27.94 -5.08); Edit 30F2010.sym; Layer 94; Wire 0.254 (-30.48 38.1) (30.48 38.1) (30.48 -38.1) (-30.48 -38.1) \ (-30.48 38.1); Pin 'VSS1' Pwr None Middle R90 Both 1 (5.08 -43.18); Pin 'VSS2' Pwr None Middle R90 Both 1 (10.16 -43.18); Layer 95; Change Size 1.905; Change Ratio 8; Text '>NAME' R0 (-29.845 38.735); Layer 96; Change Size 1.905; Change Ratio 8; Text '>VALUE' R0 (-29.845 35.56); Pin 'VDD1' Pwr None Middle R270 Both 2 (10.16 43.18); Pin 'VDD2' Pwr None Middle R270 Both 2 (15.24 43.18); Pin 'AVDD' Pwr None Middle R270 Both 0 (0 43.18); Pin 'AVSS' Pwr None Middle R90 Both 0 (-5.08 -43.18); Pin 'RB0,CN2' I/O None Middle R0 Both 0 (-35.56 22.86); Pin 'RB1,CN3' I/O None Middle R0 Both 0 (-35.56 17.78); Pin 'RB2,CN4' I/O None Middle R0 Both 0 (-35.56 12.7); Pin 'RB3,CN5' I/O None Middle R0 Both 0 (-35.56 7.62); Pin 'RB4,CN6' I/O None Middle R0 Both 0 (-35.56 2.54); Pin 'RB5,CN7' I/O None Middle R0 Both 0 (-35.56 -2.54); Pin 'RC13,CN1' I/O None Middle R0 Both 0 (-35.56 -10.16); Pin 'RC14,CN0' I/O None Middle R0 Both 0 (-35.56 -15.24); Pin 'RC15,OSC2,CLKO' I/O None Middle R0 Both 0 (-35.56 -20.32); Pin 'OSC1,CLKI' In None Middle R0 Both 0 (-35.56 -27.94); Pin 'RD0' I/O None Middle R180 Both 0 (35.56 30.48); Pin 'RD1' I/O None Middle R180 Both 0 (35.56 25.4); Pin 'PWM1L,RE0' I/O None Middle R180 Both 0 (35.56 17.78); Pin 'PWM1H,RE1' I/O None Middle R180 Both 0 (35.56 12.7); Pin 'PWM2L,RE2' I/O None Middle R180 Both 0 (35.56 7.62); Pin 'PWM2H,RE3' I/O None Middle R180 Both 0 (35.56 2.54); Pin 'PWM3L,RE4' I/O None Middle R180 Both 0 (35.56 -2.54); Pin 'PWM3H,RE5' I/O None Middle R180 Both 0 (35.56 -7.62); Pin 'RE8' I/O None Middle R180 Both 0 (35.56 -12.7); Pin 'RF2' I/O None Middle R180 Both 0 (35.56 -20.32); Pin 'RF3' I/O None Middle R180 Both 0 (35.56 -25.4); Pin 'MCLR' In None Middle R0 Both 0 (-35.56 30.48); Layer 94; Change Size 1.27; Change Ratio 12; Text 'AN0,VREF+,EMUD,PGD' R0 (-27.94 20.32); Layer 94; Change Size 1.27; Change Ratio 12; Text 'AN1,VREF-,EMUC,PDC' R0 (-27.94 15.24); Layer 94; Change Size 1.27; Change Ratio 12; Text 'AN2,LVDIN,SS1' R0 (-27.94 10.16); Layer 94; Change Size 1.27; Change Ratio 12; Text 'AN3,INDX' R0 (-27.94 5.08); Layer 94; Change Size 1.27; Change Ratio 12; Text 'AN4,IC7,QEA' R0 (-27.94 0); Layer 94; Change Size 1.27; Change Ratio 12; Text 'AN5,IC8,QEB' R0 (-27.94 -5.08); Layer 94; Change Size 1.27; Change Ratio 12; Text 'SOSC2,T2CK,U1ATX,EMUD1' R0 (-27.94 -12.7); Layer 94; Change Size 1.27; Change Ratio 12; Text 'SOSC1,T1CK,U1ARX,EMUC1' R0 (-27.94 -17.78); Layer 94; Change Size 1.27; Change Ratio 12; Text 'INT1,IC1,OC1,EMUC2' R180 (27.94 29.21); Layer 94; Change Size 1.27; Change Ratio 12; Text 'INT2,IC2,OC2,EMUD2' R180 (27.94 24.13); Layer 94; Change Size 1.27; Change Ratio 12; Text 'INT0,FLTA,OCFA,SCK1,EMUC3' R180 (27.94 -13.97); Layer 94; Change Size 1.27; Change Ratio 12; Text 'U1RX,SDA,SDI1,C1RX' R180 (27.94 -21.59); Layer 94; Change Size 1.27; Change Ratio 12; Text 'U1TX,SCL,SDO1,C1TX,EMUD3' R180 (27.94 -26.67); Edit 18F6520.sym; Layer 94; Wire 0.254 (25.4 66.04) (25.4 -66.04) (-25.4 -66.04) (-25.4 66.04) \ (25.4 66.04); Pin 'MCLR' In None Middle R0 Both 0 (-30.48 55.88); Pin 'RA0,AN0' I/O None Middle R0 Both 0 (-30.48 30.48); Pin 'RA1,AN1' I/O None Middle R0 Both 0 (-30.48 27.94); Pin 'RA2,AN2,VREF-' I/O None Middle R0 Both 0 (-30.48 25.4); Pin 'RA3,AN3,VREF+' I/O None Middle R0 Both 0 (-30.48 22.86); Pin 'RA4,T0CKI' I/O None Middle R0 Both 0 (-30.48 20.32); Pin 'RA5,AN4,LVDIN' I/O None Middle R0 Both 0 (-30.48 17.78); Pin 'RA6,OSC2,CLKO' I/O None Middle R0 Both 0 (-30.48 15.24); Pin 'OSC1,CLKI' In None Middle R0 Both 0 (-30.48 0); Pin 'VDD1' Pwr None Middle R270 Both 1 (0 71.12); Pin 'VDD2' Pwr None Middle R270 Both 1 (2.54 71.12); Pin 'VDD3' Pwr None Middle R270 Both 1 (5.08 71.12); Pin 'VDD4' Pwr None Middle R270 Both 1 (7.62 71.12); Pin 'AVDD' Pwr None Middle R270 Both 0 (-10.16 71.12); Pin 'VSS1' Pwr None Middle R90 Both 2 (0 -71.12); Pin 'VSS2' Pwr None Middle R90 Both 2 (2.54 -71.12); Pin 'VSS3' Pwr None Middle R90 Both 2 (5.08 -71.12); Pin 'VSS4' Pwr None Middle R90 Both 2 (7.62 -71.12); Pin 'AVSS' Pwr None Middle R90 Both 0 (-10.16 -71.12); Pin 'RF0,AN5' I/O None Middle R0 Both 0 (-30.48 -20.32); Pin 'RF1,AN6,C2OUT' I/O None Middle R0 Both 0 (-30.48 -22.86); Pin 'RF2,AN7,C1OUT' I/O None Middle R0 Both 0 (-30.48 -25.4); Pin 'RF3,AN8' I/O None Middle R0 Both 0 (-30.48 -27.94); Pin 'RF4,AN9' I/O None Middle R0 Both 0 (-30.48 -30.48); Pin 'RF5,AN10,CVREF' I/O None Middle R0 Both 0 (-30.48 -33.02); Pin 'RF6,AN11' I/O None Middle R0 Both 0 (-30.48 -35.56); Pin 'RF7,SS' I/O None Middle R0 Both 0 (-30.48 -38.1); Pin 'INT0,RB0' I/O None Middle R180 Both 0 (30.48 55.88); Pin 'INT1,RB1' I/O None Middle R180 Both 0 (30.48 53.34); Pin 'INT2,RB2' I/O None Middle R180 Both 0 (30.48 50.8); Pin 'INT3,CCP2,RB3' I/O None Middle R180 Both 0 (30.48 48.26); Pin 'RB4' I/O None Middle R180 Both 0 (30.48 45.72); Pin 'PGM,RB5' I/O None Middle R180 Both 0 (30.48 43.18); Pin 'PGC,RB6' I/O None Middle R180 Both 0 (30.48 40.64); Pin 'PGD,RB7' I/O None Middle R180 Both 0 (30.48 38.1); Pin 'T1OSO,T13CKI,RC0' I/O None Middle R180 Both 0 (30.48 30.48); Pin 'T1OSI,CCP2,RC1' I/O None Middle R180 Both 0 (30.48 27.94); Pin 'CCP1,RC2' I/O None Middle R180 Both 0 (30.48 25.4); Pin 'SCK,SCL,RC3' I/O None Middle R180 Both 0 (30.48 22.86); Pin 'SDI,SDA,RC4' I/O None Middle R180 Both 0 (30.48 20.32); Pin 'SDO,RC5' I/O None Middle R180 Both 0 (30.48 17.78); Pin 'TX1,CK1,RC6' I/O None Middle R180 Both 0 (30.48 15.24); Pin 'RX1,DT1,RC7' I/O None Middle R180 Both 0 (30.48 12.7); Pin 'PSP0,RD0' I/O None Middle R180 Both 0 (30.48 5.08); Pin 'PSP1,RD1' I/O None Middle R180 Both 0 (30.48 2.54); Pin 'PSP2,RD2' I/O None Middle R180 Both 0 (30.48 0); Pin 'PSP3,RD3' I/O None Middle R180 Both 0 (30.48 -2.54); Pin 'PSP4,RD4' I/O None Middle R180 Both 0 (30.48 -5.08); Pin 'PSP5,RD5' I/O None Middle R180 Both 0 (30.48 -7.62); Pin 'PSP6,RD6' I/O None Middle R180 Both 0 (30.48 -10.16); Pin 'PSP7,RD7' I/O None Middle R180 Both 0 (30.48 -12.7); Pin 'RD,RE0' I/O None Middle R180 Both 0 (30.48 -20.32); Pin 'WR,RE1' I/O None Middle R180 Both 0 (30.48 -22.86); Pin 'CS,RE2' I/O None Middle R180 Both 0 (30.48 -25.4); Pin 'RE3' I/O None Middle R180 Both 0 (30.48 -27.94); Pin 'RE4' I/O None Middle R180 Both 0 (30.48 -30.48); Pin 'RE5' I/O None Middle R180 Both 0 (30.48 -33.02); Pin 'RE6' I/O None Middle R180 Both 0 (30.48 -35.56); Pin 'CCP2,RE7' I/O None Middle R180 Both 0 (30.48 -38.1); Pin 'CCP3,RG0' I/O None Middle R180 Both 0 (30.48 -45.72); Pin 'TX2,CK2,RG1' I/O None Middle R180 Both 0 (30.48 -48.26); Pin 'RX2,DT2,RG2' I/O None Middle R180 Both 0 (30.48 -50.8); Pin 'CCP4,RG3' I/O None Middle R180 Both 0 (30.48 -53.34); Pin 'CCP5,RG4' I/O None Middle R180 Both 0 (30.48 -55.88); Layer 95; Change Size 1.905; Change Ratio 8; Text '>NAME' R0 (-25.4 66.675); Layer 95; Change Size 1.905; Change Ratio 8; Text '>VALUE' R0 (-24.13 43.18); Edit 30F6010.sym; Layer 94; Wire 0.254 (30.48 71.12) (-30.48 71.12) (-30.48 -71.12) (30.48 -71.12); Wire 0.254 (30.48 71.12) (30.48 -71.12); Pin 'VDD1' Pwr None Middle R270 Both 1 (-2.54 76.2); Pin 'VDD2' Pwr None Middle R270 Both 1 (0 76.2); Pin 'VDD3' Pwr None Middle R270 Both 1 (2.54 76.2); Pin 'VDD4' Pwr None Middle R270 Both 1 (5.08 76.2); Pin 'VSS1' Pwr None Middle R90 Both 2 (-2.54 -76.2); Pin 'VSS2' Pwr None Middle R90 Both 2 (0 -76.2); Pin 'VSS3' Pwr None Middle R90 Both 2 (2.54 -76.2); Pin 'VSS4' Pwr None Middle R90 Both 2 (5.08 -76.2); Pin 'MCLR' In None Middle R0 Both 0 (-35.56 48.26); Pin 'AVDD' Pwr None Middle R270 Both 0 (-12.7 76.2); Pin 'AVSS' Pwr None Middle R90 Both 0 (-12.7 -76.2); Pin 'OSC1,CLKI' I/O None Middle R0 Both 0 (-35.56 -48.26); Pin 'RC1,T2CK' I/O None Middle R0 Both 0 (-35.56 -27.94); Pin 'RC3,T2CK' I/O None Middle R0 Both 0 (-35.56 -30.48); Pin 'RC13,CN1,SOSC2,EMUD1' I/O None Middle R0 Both 0 (-35.56 -33.02); Pin 'RC14,CN0,SOSC1,T1CK,EMUC1' I/O None Middle R0 Both 0 (-35.56 -35.56); Pin 'RC15,OSC2,CLK0' I/O None Middle R0 Both 0 (-35.56 -38.1); Pin 'RA9,VREF-' I/O None Middle R0 Both 0 (-35.56 38.1); Pin 'RA10,VREF+' I/O None Middle R0 Both 0 (-35.56 35.56); Pin 'RA14,INT3' I/O None Middle R0 Both 0 (-35.56 33.02); Pin 'RA15,INT4' I/O None Middle R0 Both 0 (-35.56 30.48); Pin 'RB0,AN0,CN2,PGD,EMUD' I/O None Middle R0 Both 0 (-35.56 20.32); Pin 'RB1,AN1,CN3,PGC,EMUC' I/O None Middle R0 Both 0 (-35.56 17.78); Pin 'RB2,AN2,CN4,LVDIN,SS1' I/O None Middle R0 Both 0 (-35.56 15.24); Pin 'RB3,AN3,CN5,INDX' I/O None Middle R0 Both 0 (-35.56 12.7); Pin 'RB4,AN4,CN6,QEA' I/O None Middle R0 Both 0 (-35.56 10.16); Pin 'RB5,AN5,CN7,QEB' I/O None Middle R0 Both 0 (-35.56 7.62); Pin 'RB6,AN6,OCFA' I/O None Middle R0 Both 0 (-35.56 5.08); Pin 'RB7,AN7' I/O None Middle R0 Both 0 (-35.56 2.54); Pin 'RB8,AN8' I/O None Middle R0 Both 0 (-35.56 0); Pin 'RB9,AN9' I/O None Middle R0 Both 0 (-35.56 -2.54); Pin 'RB10,AN10' I/O None Middle R0 Both 0 (-35.56 -5.08); Pin 'RB11,AN11' I/O None Middle R0 Both 0 (-35.56 -7.62); Pin 'RB12,AN12' I/O None Middle R0 Both 0 (-35.56 -10.16); Pin 'RB13,AN13' I/O None Middle R0 Both 0 (-35.56 -12.7); Pin 'RB14,AN14' I/O None Middle R0 Both 0 (-35.56 -15.24); Pin 'RB15,AN15,CN12,OCFB' I/O None Middle R0 Both 0 (-35.56 -17.78); Pin 'RD0,OC1,EMUC2' I/O None Middle R180 Both 0 (35.56 60.96); Pin 'RD1,OC2,EMUD2' I/O None Middle R180 Both 0 (35.56 58.42); Pin 'RD2,OC3' I/O None Middle R180 Both 0 (35.56 55.88); Pin 'RD3,OC4' I/O None Middle R180 Both 0 (35.56 53.34); Pin 'RD4,CN13,OC5' I/O None Middle R180 Both 0 (35.56 50.8); Pin 'RD5,CN14,OC6' I/O None Middle R180 Both 0 (35.56 48.26); Pin 'RD6,CN15,OC7' I/O None Middle R180 Both 0 (35.56 45.72); Pin 'RD7,CN16,OC8,UPDN' I/O None Middle R180 Both 0 (35.56 43.18); Pin 'RD8,IC1' I/O None Middle R180 Both 0 (35.56 40.64); Pin 'RD9,IC2' I/O None Middle R180 Both 0 (35.56 38.1); Pin 'RD10,IC3' I/O None Middle R180 Both 0 (35.56 35.56); Pin 'RD11,IC4' I/O None Middle R180 Both 0 (35.56 33.02); Pin 'RD12,IC5' I/O None Middle R180 Both 0 (35.56 30.48); Pin 'RD13,CN19,IC6' I/O None Middle R180 Both 0 (35.56 27.94); Pin 'RD14,CN20,IC7' I/O None Middle R180 Both 0 (35.56 25.4); Pin 'RD15,CN21,IC8' I/O None Middle R180 Both 0 (35.56 22.86); Pin 'RE0,PWM1L' I/O None Middle R180 Both 0 (35.56 15.24); Pin 'RE1,PWM1H' I/O None Middle R180 Both 0 (35.56 12.7); Pin 'RE2,PWM2L' I/O None Middle R180 Both 0 (35.56 10.16); Pin 'RE3,PWM2H' I/O None Middle R180 Both 0 (35.56 7.62); Pin 'RE4,PWM3L' I/O None Middle R180 Both 0 (35.56 5.08); Pin 'RE5,PWM3H' I/O None Middle R180 Both 0 (35.56 2.54); Pin 'RE6,PWM4L' I/O None Middle R180 Both 0 (35.56 0); Pin 'RE7,PWM4H' I/O None Middle R180 Both 0 (35.56 -2.54); Pin 'RE8,FLTA,INT1' I/O None Middle R180 Both 0 (35.56 -5.08); Pin 'RE9,FLTB,INT2' I/O None Middle R180 Both 0 (35.56 -7.62); Pin 'RG0,C2RX' I/O None Middle R180 Both 0 (35.56 -43.18); Pin 'RG1,C2TX' I/O None Middle R180 Both 0 (35.56 -45.72); Pin 'RG2,SCL' I/O None Middle R180 Both 0 (35.56 -48.26); Pin 'RG3,SDA' I/O None Middle R180 Both 0 (35.56 -50.8); Pin 'RG6,CN8,SCK2' I/O None Middle R180 Both 0 (35.56 -53.34); Pin 'RG7,CN9,SD12' I/O None Middle R180 Both 0 (35.56 -55.88); Pin 'RG8,CN10,SDO2' I/O None Middle R180 Both 0 (35.56 -58.42); Pin 'RG9,CN11,SS2' I/O None Middle R180 Both 0 (35.56 -60.96); Pin 'RF0,C1RX' I/O None Middle R180 Both 0 (35.56 -15.24); Pin 'RF1,C1TX' I/O None Middle R180 Both 0 (35.56 -17.78); Pin 'RF2,U1RX' I/O None Middle R180 Both 0 (35.56 -20.32); Pin 'RF3,U1TX' I/O None Middle R180 Both 0 (35.56 -22.86); Pin 'RF4,CN17,U2RX' I/O None Middle R180 Both 0 (35.56 -25.4); Pin 'RF5,CN18,U2TX' I/O None Middle R180 Both 0 (35.56 -27.94); Pin 'RF6,INT0,SCK1,EMUC3' I/O None Middle R180 Both 0 (35.56 -30.48); Pin 'RF7,SDI1' I/O None Middle R180 Both 0 (35.56 -33.02); Pin 'RF8,SD01,EMUD3' I/O None Middle R180 Both 0 (35.56 -35.56); Layer 95; Change Size 1.905; Change Ratio 8; Text '>NAME' R0 (-29.845 71.755); Layer 96; Change Size 1.905; Change Ratio 8; Text '>VALUE' R0 (-29.21 57.15); Edit 10F204.sym; Pin 'VDD' Pwr None Middle R270 Both 0 (12.7 17.78); Pin 'VSS' Pwr None Middle R90 Both 0 (0 -20.32); Pin 'GP3/MCLR' In None Middle R0 Both 0 (-20.32 -5.08); Pin 'GP0/CIN+/PGD' I/O None Middle R0 Both 0 (-20.32 2.54); Pin 'GP1/CIN-/PGC' I/O None Middle R0 Both 0 (-20.32 0); Pin 'GP2/COUT/T0CKI/FOSC4' I/O None Middle R0 Both 0 (-20.32 -2.54); Layer 94; Wire 0.254 (-15.24 12.7) (-15.24 -15.24) (15.24 -15.24) (15.24 12.7) \ (-15.24 12.7); Layer 95; Change Size 1.905; Change Ratio 8; Text '>NAME' R0 (-15.24 13.335); Layer 96; Change Size 1.905; Change Ratio 8; Text '>VALUE' R0 (-14.605 10.16); Edit 30F4011.sym; Pin 'VDD1' Pwr None Middle R270 Both 1 (5.08 48.26); Pin 'VDD2' Pwr None Middle R270 Both 1 (7.62 48.26); Pin 'VDD3' Pwr None Middle R270 Both 1 (10.16 48.26); Pin 'AVDD' Pwr None Middle R270 Both 0 (-7.62 48.26); Layer 94; Wire 0.254 (-30.48 43.18) (30.48 43.18); Wire 0.254 (-30.48 -43.18) (30.48 -43.18); Wire 0.254 (-30.48 43.18) (-30.48 -43.18); Wire 0.254 (30.48 -43.18) (30.48 43.18); Layer 95; Change Size 1.905; Change Ratio 8; Text '>NAME' R0 (-29.845 43.815); Pin 'VSS1' Pwr None Middle R90 Both 2 (5.08 -48.26); Pin 'VSS2' Pwr None Middle R90 Both 2 (7.62 -48.26); Pin 'VSS3' Pwr None Middle R90 Both 2 (10.16 -48.26); Pin 'AVSS' Pwr None Middle R90 Both 0 (-7.62 -48.26); Pin 'MCLR' In None Middle R0 Both 0 (-35.56 25.4); Pin 'RB0,AN0,VREF+,CN2,EMUD3' I/O None Middle R0 Both 0 (-35.56 15.24); Pin 'RB1,AN1,VREF-,CN3,EMUC3' I/O None Middle R0 Both 0 (-35.56 12.7); Pin 'RB2,AN2,CN4,SS1' I/O None Middle R0 Both 0 (-35.56 10.16); Pin 'RB3,AN3,CN5,INDX' I/O None Middle R0 Both 0 (-35.56 7.62); Pin 'RB4,AN4,CN6,IC7,QEA' I/O None Middle R0 Both 0 (-35.56 5.08); Pin 'RB5,AN5,CN7,IC8,QEB' I/O None Middle R0 Both 0 (-35.56 2.54); Pin 'RB6,AN6,OCFA' I/O None Middle R0 Both 0 (-35.56 0); Pin 'RB7,AN7' I/O None Middle R0 Both 0 (-35.56 -2.54); Pin 'RB8,AN8' I/O None Middle R0 Both 0 (-35.56 -5.08); Pin 'RC14,CN0,U1ARX,T1CK,SOSCO,EMUC1' I/O None Middle R0 Both 0 (-35.56 -17.78); Pin 'RC13,CN1,U1ATX,T2CK,SOSCI,EMUD1' I/O None Middle R0 Both 0 (-35.56 -15.24); Pin 'RC15,OSC2,CLKO' I/O None Middle R0 Both 0 (-35.56 -20.32); Pin 'OSC1,CLKIN' In None Middle R0 Both 0 (-35.56 -30.48); Pin 'RD1,INT2,IC2,OC2,EMUD2' I/O None Middle R180 Both 0 (35.56 22.86); Pin 'RD0,INT1,IC1,OC1,EMUC2' I/O None Middle R180 Both 0 (35.56 25.4); Pin 'RD2,OC3' I/O None Middle R180 Both 0 (35.56 20.32); Pin 'RD3,OC4' I/O None Middle R180 Both 0 (35.56 17.78); Pin 'RE0,PWM1L' I/O None Middle R180 Both 0 (35.56 7.62); Pin 'RE1,PWM1H' I/O None Middle R180 Both 0 (35.56 5.08); Pin 'RE2,PWM2L' I/O None Middle R180 Both 0 (35.56 2.54); Pin 'RE3,PWM2H' I/O None Middle R180 Both 0 (35.56 0); Pin 'RE4,PWM3L' I/O None Middle R180 Both 0 (35.56 -2.54); Pin 'RE5,PWM3H' I/O None Middle R180 Both 0 (35.56 -5.08); Pin 'RF0,CRX1' I/O None Middle R180 Both 0 (35.56 -17.78); Pin 'RF1,CTX1' I/O None Middle R180 Both 0 (35.56 -20.32); Pin 'RF2,U1RX,SDA,SDI1,PGC,EMUC' I/O None Middle R180 Both 0 (35.56 -22.86); Pin 'RF4,U2RX,CN17' I/O None Middle R180 Both 0 (35.56 -27.94); Pin 'RF5,U2TX,CN18' I/O None Middle R180 Both 0 (35.56 -30.48); Pin 'RF3,U1TX,SCL,SDO1,PGD,EMUD' I/O None Middle R180 Both 0 (35.56 -25.4); Pin 'RF6,SCK1' I/O None Middle R180 Both 0 (35.56 -33.02); Pin 'RE8,INT0,FLTA' I/O None Middle R180 Both 0 (35.56 -7.62); Layer 96; Change Size 1.905; Change Ratio 8; Text '>VALUE' R0 (-27.94 30.48); Edit 10F200.sym; Pin 'VDD' Pwr None Middle R270 Both 0 (12.7 17.78); Pin 'VSS' Pwr None Middle R90 Both 0 (0 -20.32); Pin 'GP3/MCLR' In None Middle R0 Both 0 (-20.32 -5.08); Pin 'GP0/PGD' I/O None Middle R0 Both 0 (-20.32 2.54); Pin 'GP1/PGC' I/O None Middle R0 Both 0 (-20.32 0); Pin 'GP2/T0CKI/FOSC4' I/O None Middle R0 Both 0 (-20.32 -2.54); Layer 94; Wire 0.254 (-15.24 12.7) (-15.24 -15.24) (15.24 -15.24) (15.24 12.7) \ (-15.24 12.7); Layer 95; Change Size 1.905; Change Ratio 8; Text '>NAME' R0 (-15.24 13.335); Layer 96; Change Size 1.905; Change Ratio 8; Text '>VALUE' R0 (-14.605 10.16); Edit 30F4012.sym; Layer 94; Wire 0.254 (-30.48 38.1) (30.48 38.1) (30.48 -38.1) (-30.48 -38.1) \ (-30.48 38.1); Pin 'VSS1' Pwr None Middle R90 Both 1 (2.54 -43.18); Pin 'VSS2' Pwr None Middle R90 Both 1 (7.62 -43.18); Layer 95; Change Size 1.905; Change Ratio 8; Text '>NAME' R0 (-29.845 38.735); Layer 96; Change Size 1.905; Change Ratio 8; Text '>VALUE' R0 (-25.4 25.7175); Pin 'VDD1' Pwr None Middle R270 Both 2 (2.54 43.18); Pin 'VDD2' Pwr None Middle R270 Both 2 (7.62 43.18); Pin 'AVDD' Pwr None Middle R270 Both 0 (-7.62 43.18); Pin 'AVSS' Pwr None Middle R90 Both 0 (-7.62 -43.18); Pin 'RB0,CN2' I/O None Middle R0 Both 0 (-35.56 22.86); Pin 'RB1,CN3' I/O None Middle R0 Both 0 (-35.56 17.78); Pin 'RB2,CN4' I/O None Middle R0 Both 0 (-35.56 12.7); Pin 'RB3,CN5' I/O None Middle R0 Both 0 (-35.56 7.62); Pin 'RB4,CN6' I/O None Middle R0 Both 0 (-35.56 2.54); Pin 'RB5,CN7' I/O None Middle R0 Both 0 (-35.56 -2.54); Pin 'RC13,CN1' I/O None Middle R0 Both 0 (-35.56 -10.16); Pin 'RC14,CN0' I/O None Middle R0 Both 0 (-35.56 -15.24); Pin 'RC15,OSC2,CLKO' I/O None Middle R0 Both 0 (-35.56 -20.32); Pin 'OSC1,CLKI' In None Middle R0 Both 0 (-35.56 -27.94); Pin 'RD0,INT1' I/O None Middle R180 Both 0 (35.56 30.48); Pin 'RD1,INT2' I/O None Middle R180 Both 0 (35.56 25.4); Pin 'PWM1L,RE0' I/O None Middle R180 Both 0 (35.56 17.78); Pin 'PWM1H,RE1' I/O None Middle R180 Both 0 (35.56 12.7); Pin 'PWM2L,RE2' I/O None Middle R180 Both 0 (35.56 7.62); Pin 'PWM2H,RE3' I/O None Middle R180 Both 0 (35.56 2.54); Pin 'PWM3L,RE4' I/O None Middle R180 Both 0 (35.56 -2.54); Pin 'PWM3H,RE5' I/O None Middle R180 Both 0 (35.56 -7.62); Pin 'RE8,INT0' I/O None Middle R180 Both 0 (35.56 -12.7); Pin 'RF2,PGC,EMUC' I/O None Middle R180 Both 0 (35.56 -20.32); Pin 'RF3,PGD,EMUD' I/O None Middle R180 Both 0 (35.56 -25.4); Pin 'MCLR' In None Middle R0 Both 0 (-35.56 30.48); Layer 94; Change Size 1.524; Change Ratio 9; Text 'AN4,IC7,QEA' R0 (-27.94 0); Layer 94; Change Size 1.524; Change Ratio 9; Text 'AN5,IC8,QEB' R0 (-27.94 -5.08); Layer 94; Change Size 1.524; Change Ratio 9; Text 'AN0,Vref+,EMUD3' R0 (-27.94 20.32); Layer 94; Change Size 1.524; Change Ratio 9; Text 'AN1,Vref-,EMUC3' R0 (-27.94 15.24); Layer 94; Change Size 1.524; Change Ratio 9; Text 'AN2,SS1' R0 (-27.94 10.16); Layer 94; Change Size 1.524; Change Ratio 9; Text 'AN3,INDX' R0 (-27.94 5.08); Layer 94; Change Size 1.524; Change Ratio 9; Text 'SOSCI,T2CK,U1ATX,EMUD1' R0 (-27.94 -12.7); Layer 94; Change Size 1.524; Change Ratio 9; Text 'SOSCO,T1CK,U1ARX,EMUC1' R0 (-27.94 -17.78); Layer 94; Change Size 1.524; Change Ratio 9; Text 'OC1,IC1,EMUC2' R180 (27.94 29.21); Layer 94; Change Size 1.524; Change Ratio 9; Text 'OC2,IC2,EMUD2' R180 (27.94 24.13); Layer 94; Change Size 1.524; Change Ratio 9; Text 'FLTA,OCFA,SCK1' R180 (27.94 -13.97); Layer 94; Change Size 1.524; Change Ratio 9; Text 'U1RX,SDA,SDI1,C1RX' R180 (27.94 -21.59); Layer 94; Change Size 1.524; Change Ratio 9; Text 'U1TX,SCL,SDO1,C1TX' R180 (27.94 -26.67); Edit PDIP-28.pac; Description '28 pin skinny DIP (SP suffix)'; Change Drill 0.7366;Pad '1' Square 1.524 R0 (-17.78 -3.81); Change Drill 0.7366;Pad '2' Round 1.524 R0 (-15.24 -3.81); Change Drill 0.7366;Pad '3' Round 1.524 R0 (-12.7 -3.81); Change Drill 0.7366;Pad '4' Round 1.524 R0 (-10.16 -3.81); Change Drill 0.7366;Pad '5' Round 1.524 R0 (-7.62 -3.81); Change Drill 0.7366;Pad '6' Round 1.524 R0 (-5.08 -3.81); Change Drill 0.7366;Pad '7' Round 1.524 R0 (-2.54 -3.81); Change Drill 0.7366;Pad '8' Round 1.524 R0 (0 -3.81); Change Drill 0.7366;Pad '9' Round 1.524 R0 (2.54 -3.81); Change Drill 0.7366;Pad '10' Round 1.524 R0 (5.08 -3.81); Change Drill 0.7366;Pad '11' Round 1.524 R0 (7.62 -3.81); Change Drill 0.7366;Pad '12' Round 1.524 R0 (10.16 -3.81); Change Drill 0.7366;Pad '13' Round 1.524 R0 (12.7 -3.81); Change Drill 0.7366;Pad '14' Round 1.524 R0 (15.24 -3.81); Change Drill 0.7366;Pad '15' Round 1.524 R0 (15.24 3.81); Change Drill 0.7366;Pad '16' Round 1.524 R0 (12.7 3.81); Change Drill 0.7366;Pad '17' Round 1.524 R0 (10.16 3.81); Change Drill 0.7366;Pad '18' Round 1.524 R0 (7.62 3.81); Change Drill 0.7366;Pad '19' Round 1.524 R0 (5.08 3.81); Change Drill 0.7366;Pad '20' Round 1.524 R0 (2.54 3.81); Change Drill 0.7366;Pad '21' Round 1.524 R0 (0 3.81); Change Drill 0.7366;Pad '22' Round 1.524 R0 (-2.54 3.81); Change Drill 0.7366;Pad '23' Round 1.524 R0 (-5.08 3.81); Change Drill 0.7366;Pad '24' Round 1.524 R0 (-7.62 3.81); Change Drill 0.7366;Pad '25' Round 1.524 R0 (-10.16 3.81); Change Drill 0.7366;Pad '26' Round 1.524 R0 (-12.7 3.81); Change Drill 0.7366;Pad '27' Round 1.524 R0 (-15.24 3.81); Change Drill 0.7366;Pad '28' Round 1.524 R0 (-17.78 3.81); Layer 21; Wire 0.254 (-19.05 -2.54) (16.51 -2.54) (16.51 2.54) (-19.05 2.54); Wire 0.254 (-19.05 -1.27) +180 (-19.05 1.27); Wire 0.254 (-19.05 2.54) (-19.05 1.27); Wire 0.254 (-19.05 -1.27) (-19.05 -2.54); Layer 25; Change Size 1.524; Change Ratio 14; Text '>NAME' R90 (-19.3675 -1.27); Layer 25; Change Size 1.524; Change Ratio 14; Text '>NAME' R0 (-5.08 0.3175); Layer 27; Change Size 1.524; Change Ratio 14; Text '>VALUE' R0 (-15.24 -1.905); Edit DIP-40.pac; Description '40 pin DIP, P or PL suffix'; Change Drill 0.7366;Pad '1' Square 1.524 R0 (-24.13 -7.62); Change Drill 0.7366;Pad '2' Round 1.524 R0 (-21.59 -7.62); Change Drill 0.7366;Pad '3' Round 1.524 R0 (-19.05 -7.62); Change Drill 0.7366;Pad '4' Round 1.524 R0 (-16.51 -7.62); Change Drill 0.7366;Pad '5' Round 1.524 R0 (-13.97 -7.62); Change Drill 0.7366;Pad '6' Round 1.524 R0 (-11.43 -7.62); Change Drill 0.7366;Pad '7' Round 1.524 R0 (-8.89 -7.62); Change Drill 0.7366;Pad '8' Round 1.524 R0 (-6.35 -7.62); Change Drill 0.7366;Pad '9' Round 1.524 R0 (-3.81 -7.62); Change Drill 0.7366;Pad '10' Round 1.524 R0 (-1.27 -7.62); Change Drill 0.7366;Pad '11' Round 1.524 R0 (1.27 -7.62); Change Drill 0.7366;Pad '12' Round 1.524 R0 (3.81 -7.62); Change Drill 0.7366;Pad '13' Round 1.524 R0 (6.35 -7.62); Change Drill 0.7366;Pad '14' Round 1.524 R0 (8.89 -7.62); Change Drill 0.7366;Pad '15' Round 1.524 R0 (11.43 -7.62); Change Drill 0.7366;Pad '16' Round 1.524 R0 (13.97 -7.62); Change Drill 0.7366;Pad '17' Round 1.524 R0 (16.51 -7.62); Change Drill 0.7366;Pad '18' Round 1.524 R0 (19.05 -7.62); Change Drill 0.7366;Pad '19' Round 1.524 R0 (21.59 -7.62); Change Drill 0.7366;Pad '20' Round 1.524 R0 (24.13 -7.62); Change Drill 0.7366;Pad '21' Round 1.524 R0 (24.13 7.62); Change Drill 0.7366;Pad '22' Round 1.524 R0 (21.59 7.62); Change Drill 0.7366;Pad '23' Round 1.524 R0 (19.05 7.62); Change Drill 0.7366;Pad '24' Round 1.524 R0 (16.51 7.62); Change Drill 0.7366;Pad '25' Round 1.524 R0 (13.97 7.62); Change Drill 0.7366;Pad '26' Round 1.524 R0 (11.43 7.62); Change Drill 0.7366;Pad '27' Round 1.524 R0 (8.89 7.62); Change Drill 0.7366;Pad '28' Round 1.524 R0 (6.35 7.62); Change Drill 0.7366;Pad '29' Round 1.524 R0 (3.81 7.62); Change Drill 0.7366;Pad '30' Round 1.524 R0 (1.27 7.62); Change Drill 0.7366;Pad '31' Round 1.524 R0 (-1.27 7.62); Change Drill 0.7366;Pad '32' Round 1.524 R0 (-3.81 7.62); Change Drill 0.7366;Pad '33' Round 1.524 R0 (-6.35 7.62); Change Drill 0.7366;Pad '34' Round 1.524 R0 (-8.89 7.62); Change Drill 0.7366;Pad '35' Round 1.524 R0 (-11.43 7.62); Change Drill 0.7366;Pad '36' Round 1.524 R0 (-13.97 7.62); Change Drill 0.7366;Pad '37' Round 1.524 R0 (-16.51 7.62); Change Drill 0.7366;Pad '38' Round 1.524 R0 (-19.05 7.62); Change Drill 0.7366;Pad '39' Round 1.524 R0 (-21.59 7.62); Change Drill 0.7366;Pad '40' Round 1.524 R0 (-24.13 7.62); Layer 21; Wire 0.254 (-25.4 -6.35) (25.4 -6.35) (25.4 6.35) (-25.4 6.35); Wire 0.254 (-25.4 1.27) -180 (-25.4 -1.27); Wire 0.254 (-25.4 6.35) (-25.4 1.27); Wire 0.254 (-25.4 -1.27) (-25.4 -6.35); Layer 25; Change Size 1.905; Change Ratio 13; Text '>NAME' R90 (-26.035 -2.54); Layer 27; Change Size 2.54; Change Ratio 10; Text '>VALUE' R0 (-22.86 -3.81); Layer 25; Change Size 2.54; Change Ratio 10; Text '>NAME' R0 (-22.86 1.27); Edit DIP-18.pac; Description '18 pin DIP package, P suffix'; Change Drill 0.7366;Pad '1' Square 1.524 R0 (-10.16 -3.81); Change Drill 0.7366;Pad '2' Round 1.524 R0 (-7.62 -3.81); Change Drill 0.7366;Pad '3' Round 1.524 R0 (-5.08 -3.81); Change Drill 0.7366;Pad '4' Round 1.524 R0 (-2.54 -3.81); Change Drill 0.7366;Pad '5' Round 1.524 R0 (0 -3.81); Change Drill 0.7366;Pad '6' Round 1.524 R0 (2.54 -3.81); Change Drill 0.7366;Pad '7' Round 1.524 R0 (5.08 -3.81); Change Drill 0.7366;Pad '8' Round 1.524 R0 (7.62 -3.81); Change Drill 0.7366;Pad '9' Round 1.524 R0 (10.16 -3.81); Change Drill 0.7366;Pad '10' Round 1.524 R0 (10.16 3.81); Change Drill 0.7366;Pad '11' Round 1.524 R0 (7.62 3.81); Change Drill 0.7366;Pad '12' Round 1.524 R0 (5.08 3.81); Change Drill 0.7366;Pad '13' Round 1.524 R0 (2.54 3.81); Change Drill 0.7366;Pad '14' Round 1.524 R0 (0 3.81); Change Drill 0.7366;Pad '15' Round 1.524 R0 (-2.54 3.81); Change Drill 0.7366;Pad '16' Round 1.524 R0 (-5.08 3.81); Change Drill 0.7366;Pad '17' Round 1.524 R0 (-7.62 3.81); Change Drill 0.7366;Pad '18' Round 1.524 R0 (-10.16 3.81); Layer 21; Wire 0.254 (-11.43 -2.54) (11.43 -2.54) (11.43 2.54) (-11.43 2.54); Wire 0.254 (-11.43 -1.27) +180 (-11.43 1.27); Layer 25; Change Size 1.524; Change Ratio 14; Text '>NAME' R90 (-12.065 -2.54); Layer 21; Wire 0.254 (-11.43 2.54) (-11.43 1.27); Wire 0.254 (-11.43 -1.27) (-11.43 -2.54); Layer 27; Change Size 1.524; Change Ratio 14; Text '>VALUE' R0 (-9.2075 -0.635); Edit DIP-8.pac; Description '8 Pin DIP'; Change Drill 0.7366;Pad '1' Square 1.524 R0 (-3.81 -3.81); Change Drill 0.7366;Pad '2' Round 1.524 R0 (-1.27 -3.81); Change Drill 0.7366;Pad '3' Round 1.524 R0 (1.27 -3.81); Change Drill 0.7366;Pad '4' Round 1.524 R0 (3.81 -3.81); Change Drill 0.7366;Pad '5' Round 1.524 R0 (3.81 3.81); Change Drill 0.7366;Pad '6' Round 1.524 R0 (1.27 3.81); Change Drill 0.7366;Pad '7' Round 1.524 R0 (-1.27 3.81); Change Drill 0.7366;Pad '8' Round 1.524 R0 (-3.81 3.81); Layer 21; Wire 0.254 (-5.08 -2.54) (5.08 -2.54) (5.08 2.54) (-5.08 2.54); Layer 25; Change Size 1.524; Change Ratio 14; Text '>NAME' R90 (-5.3975 -1.5875); Layer 21; Wire 0.254 (-5.08 -1.016) +180 (-5.08 1.016); Wire 0.254 (-5.08 2.54) (-5.08 1.016); Wire 0.254 (-5.08 -1.016) (-5.08 -2.54); Edit DIP-14.pac; Description '14 pin DIP package, P suffix'; Change Drill 0.7366;Pad '1' Square 1.524 R0 (-10.16 -3.81); Change Drill 0.7366;Pad '2' Round 1.524 R0 (-7.62 -3.81); Change Drill 0.7366;Pad '3' Round 1.524 R0 (-5.08 -3.81); Change Drill 0.7366;Pad '4' Round 1.524 R0 (-2.54 -3.81); Change Drill 0.7366;Pad '5' Round 1.524 R0 (0 -3.81); Change Drill 0.7366;Pad '6' Round 1.524 R0 (2.54 -3.81); Change Drill 0.7366;Pad '7' Round 1.524 R0 (5.08 -3.81); Change Drill 0.7366;Pad '8' Round 1.524 R0 (5.08 3.81); Change Drill 0.7366;Pad '9' Round 1.524 R0 (2.54 3.81); Change Drill 0.7366;Pad '10' Round 1.524 R0 (0 3.81); Change Drill 0.7366;Pad '11' Round 1.524 R0 (-2.54 3.81); Change Drill 0.7366;Pad '12' Round 1.524 R0 (-5.08 3.81); Change Drill 0.7366;Pad '13' Round 1.524 R0 (-7.62 3.81); Change Drill 0.7366;Pad '14' Round 1.524 R0 (-10.16 3.81); Layer 21; Wire 0.254 (-11.43 -2.54) (6.35 -2.54) (6.35 2.54) (-11.43 2.54); Wire 0.254 (-11.43 -1.27) +180 (-11.43 1.27); Layer 25; Change Size 1.524; Change Ratio 14; Text '>NAME' R90 (-11.7475 -1.27); Layer 27; Change Size 1.27; Change Ratio 16; Text '>VALUE' R0 (-9.8425 -1.905); Layer 21; Wire 0.254 (-11.43 2.54) (-11.43 1.27); Wire 0.254 (-11.43 -1.27) (-11.43 -2.54); Layer 25; Change Size 1.27; Change Ratio 16; Text '>NAME' R0 (-5.08 0.635); Edit TQFP-64.pac; Description '64 pin TQFP (PT suffix)'; Layer 1; Smd '1' 1.25 0.25 -0 R0 (-5.625 3.75); Layer 1; Smd '2' 1.25 0.25 -0 R0 (-5.625 3.25); Layer 1; Smd '3' 1.25 0.25 -0 R0 (-5.625 2.75); Layer 1; Smd '4' 1.25 0.25 -0 R0 (-5.625 2.25); Layer 1; Smd '5' 1.25 0.25 -0 R0 (-5.625 1.75); Layer 1; Smd '6' 1.25 0.25 -0 R0 (-5.625 1.25); Layer 1; Smd '7' 1.25 0.25 -0 R0 (-5.625 0.75); Layer 1; Smd '8' 1.25 0.25 -0 R0 (-5.625 0.25); Layer 1; Smd '9' 1.25 0.25 -0 R0 (-5.625 -0.25); Layer 1; Smd '10' 1.25 0.25 -0 R0 (-5.625 -0.75); Layer 1; Smd '11' 1.25 0.25 -0 R0 (-5.625 -1.25); Layer 1; Smd '12' 1.25 0.25 -0 R0 (-5.625 -1.75); Layer 1; Smd '13' 1.25 0.25 -0 R0 (-5.625 -2.25); Layer 1; Smd '14' 1.25 0.25 -0 R0 (-5.625 -2.75); Layer 1; Smd '15' 1.25 0.25 -0 R0 (-5.625 -3.25); Layer 1; Smd '16' 1.25 0.25 -0 R0 (-5.625 -3.75); Layer 1; Smd '17' 0.25 1.25 -0 R0 (-3.75 -5.625); Layer 1; Smd '18' 0.25 1.25 -0 R0 (-3.25 -5.625); Layer 1; Smd '19' 0.25 1.25 -0 R0 (-2.75 -5.625); Layer 1; Smd '20' 0.25 1.25 -0 R0 (-2.25 -5.625); Layer 1; Smd '21' 0.25 1.25 -0 R0 (-1.75 -5.625); Layer 1; Smd '22' 0.25 1.25 -0 R0 (-1.25 -5.625); Layer 1; Smd '23' 0.25 1.25 -0 R0 (-0.75 -5.625); Layer 1; Smd '24' 0.25 1.25 -0 R0 (-0.25 -5.625); Layer 1; Smd '25' 0.25 1.25 -0 R0 (0.25 -5.625); Layer 1; Smd '26' 0.25 1.25 -0 R0 (0.75 -5.625); Layer 1; Smd '27' 0.25 1.25 -0 R0 (1.25 -5.625); Layer 1; Smd '28' 0.25 1.25 -0 R0 (1.75 -5.625); Layer 1; Smd '29' 0.25 1.25 -0 R0 (2.25 -5.625); Layer 1; Smd '30' 0.25 1.25 -0 R0 (2.75 -5.625); Layer 1; Smd '31' 0.25 1.25 -0 R0 (3.25 -5.625); Layer 1; Smd '32' 0.25 1.25 -0 R0 (3.75 -5.625); Layer 1; Smd '33' 1.25 0.25 -0 R0 (5.625 -3.75); Layer 1; Smd '34' 1.25 0.25 -0 R0 (5.625 -3.25); Layer 1; Smd '35' 1.25 0.25 -0 R0 (5.625 -2.75); Layer 1; Smd '36' 1.25 0.25 -0 R0 (5.625 -2.25); Layer 1; Smd '37' 1.25 0.25 -0 R0 (5.625 -1.75); Layer 1; Smd '38' 1.25 0.25 -0 R0 (5.625 -1.25); Layer 1; Smd '39' 1.25 0.25 -0 R0 (5.625 -0.75); Layer 1; Smd '40' 1.25 0.25 -0 R0 (5.625 -0.25); Layer 1; Smd '41' 1.25 0.25 -0 R0 (5.625 0.25); Layer 1; Smd '42' 1.25 0.25 -0 R0 (5.625 0.75); Layer 1; Smd '43' 1.25 0.25 -0 R0 (5.625 1.25); Layer 1; Smd '44' 1.25 0.25 -0 R0 (5.625 1.75); Layer 1; Smd '45' 1.25 0.25 -0 R0 (5.625 2.25); Layer 1; Smd '46' 1.25 0.25 -0 R0 (5.625 2.75); Layer 1; Smd '47' 1.25 0.25 -0 R0 (5.625 3.25); Layer 1; Smd '48' 1.25 0.25 -0 R0 (5.625 3.75); Layer 1; Smd '49' 0.25 1.25 -0 R0 (3.75 5.625); Layer 1; Smd '50' 0.25 1.25 -0 R0 (3.25 5.625); Layer 1; Smd '51' 0.25 1.25 -0 R0 (2.75 5.625); Layer 1; Smd '52' 0.25 1.25 -0 R0 (2.25 5.625); Layer 1; Smd '53' 0.25 1.25 -0 R0 (1.75 5.625); Layer 1; Smd '54' 0.25 1.25 -0 R0 (1.25 5.625); Layer 1; Smd '55' 0.25 1.25 -0 R0 (0.75 5.625); Layer 1; Smd '56' 0.25 1.25 -0 R0 (0.25 5.625); Layer 1; Smd '57' 0.25 1.25 -0 R0 (-0.25 5.625); Layer 1; Smd '58' 0.25 1.25 -0 R0 (-0.75 5.625); Layer 1; Smd '59' 0.25 1.25 -0 R0 (-1.25 5.625); Layer 1; Smd '60' 0.25 1.25 -0 R0 (-1.75 5.625); Layer 1; Smd '61' 0.25 1.25 -0 R0 (-2.25 5.625); Layer 1; Smd '62' 0.25 1.25 -0 R0 (-2.75 5.625); Layer 1; Smd '63' 0.25 1.25 -0 R0 (-3.25 5.625); Layer 1; Smd '64' 0.25 1.25 -0 R0 (-3.75 5.625); Layer 21; Wire 0.254 (-4.7625 3.81) (-3.81 4.7625) (4.7625 4.7625) (4.7625 -4.7625) \ (-4.7625 -4.7625) (-4.7625 3.81); Layer 21; Change Spacing 1.27; Change Pour Solid; Change Rank 0; Polygon 0.2032 (-6.6675 3.81) (-7.3025 4.1275) (-7.3025 3.4925) (-6.6675 3.81); Layer 21; Change Size 1.27; Change Ratio 16; Text '>NAME' R180 (-4.1275 5.715); Layer 21; Change Size 1.905; Change Ratio 13; Text '>NAME' R0 (-2.8575 -0.9525); Layer 21; Circle 0 (-4.1275 3.4925) (-3.81 3.4925); Edit TQFP-80-12.pac; Description '80 pin TQFP 12x12mm (PT suffix)'; Layer 1; Smd '1' 1.25 0.25 -0 R0 (-6.625 4.75); Layer 1; Smd '2' 1.25 0.25 -0 R0 (-6.625 4.25); Layer 1; Smd '3' 1.25 0.25 -0 R0 (-6.625 3.75); Layer 1; Smd '4' 1.25 0.25 -0 R0 (-6.625 3.25); Layer 1; Smd '5' 1.25 0.25 -0 R0 (-6.625 2.75); Layer 1; Smd '6' 1.25 0.25 -0 R0 (-6.625 2.25); Layer 1; Smd '7' 1.25 0.25 -0 R0 (-6.625 1.75); Layer 1; Smd '8' 1.25 0.25 -0 R0 (-6.625 1.25); Layer 1; Smd '9' 1.25 0.25 -0 R0 (-6.625 0.75); Layer 1; Smd '10' 1.25 0.25 -0 R0 (-6.625 0.25); Layer 1; Smd '11' 1.25 0.25 -0 R0 (-6.625 -0.25); Layer 1; Smd '12' 1.25 0.25 -0 R0 (-6.625 -0.75); Layer 1; Smd '13' 1.25 0.25 -0 R0 (-6.625 -1.25); Layer 1; Smd '14' 1.25 0.25 -0 R0 (-6.625 -1.75); Layer 1; Smd '15' 1.25 0.25 -0 R0 (-6.625 -2.25); Layer 1; Smd '16' 1.25 0.25 -0 R0 (-6.625 -2.75); Layer 1; Smd '17' 1.25 0.25 -0 R0 (-6.625 -3.25); Layer 1; Smd '18' 1.25 0.25 -0 R0 (-6.625 -3.75); Layer 1; Smd '19' 1.25 0.25 -0 R0 (-6.625 -4.25); Layer 1; Smd '20' 1.25 0.25 -0 R0 (-6.625 -4.75); Layer 1; Smd '21' 0.25 1.25 -0 R0 (-4.75 -6.625); Layer 1; Smd '22' 0.25 1.25 -0 R0 (-4.25 -6.625); Layer 1; Smd '23' 0.25 1.25 -0 R0 (-3.75 -6.625); Layer 1; Smd '24' 0.25 1.25 -0 R0 (-3.25 -6.625); Layer 1; Smd '25' 0.25 1.25 -0 R0 (-2.75 -6.625); Layer 1; Smd '26' 0.25 1.25 -0 R0 (-2.25 -6.625); Layer 1; Smd '27' 0.25 1.25 -0 R0 (-1.75 -6.625); Layer 1; Smd '28' 0.25 1.25 -0 R0 (-1.25 -6.625); Layer 1; Smd '29' 0.25 1.25 -0 R0 (-0.75 -6.625); Layer 1; Smd '30' 0.25 1.25 -0 R0 (-0.25 -6.625); Layer 1; Smd '31' 0.25 1.25 -0 R0 (0.25 -6.625); Layer 1; Smd '32' 0.25 1.25 -0 R0 (0.75 -6.625); Layer 1; Smd '33' 0.25 1.25 -0 R0 (1.25 -6.625); Layer 1; Smd '34' 0.25 1.25 -0 R0 (1.75 -6.625); Layer 1; Smd '35' 0.25 1.25 -0 R0 (2.25 -6.625); Layer 1; Smd '36' 0.25 1.25 -0 R0 (2.75 -6.625); Layer 1; Smd '37' 0.25 1.25 -0 R0 (3.25 -6.625); Layer 1; Smd '38' 0.25 1.25 -0 R0 (3.75 -6.625); Layer 1; Smd '39' 0.25 1.25 -0 R0 (4.25 -6.625); Layer 1; Smd '40' 0.25 1.25 -0 R0 (4.75 -6.625); Layer 1; Smd '41' 1.25 0.25 -0 R0 (6.625 -4.75); Layer 1; Smd '42' 1.25 0.25 -0 R0 (6.625 -4.25); Layer 1; Smd '43' 1.25 0.25 -0 R0 (6.625 -3.75); Layer 1; Smd '44' 1.25 0.25 -0 R0 (6.625 -3.25); Layer 1; Smd '45' 1.25 0.25 -0 R0 (6.625 -2.75); Layer 1; Smd '46' 1.25 0.25 -0 R0 (6.625 -2.25); Layer 1; Smd '47' 1.25 0.25 -0 R0 (6.625 -1.75); Layer 1; Smd '48' 1.25 0.25 -0 R0 (6.625 -1.25); Layer 1; Smd '49' 1.25 0.25 -0 R0 (6.625 -0.75); Layer 1; Smd '50' 1.25 0.25 -0 R0 (6.625 -0.25); Layer 1; Smd '51' 1.25 0.25 -0 R0 (6.625 0.25); Layer 1; Smd '52' 1.25 0.25 -0 R0 (6.625 0.75); Layer 1; Smd '53' 1.25 0.25 -0 R0 (6.625 1.25); Layer 1; Smd '54' 1.25 0.25 -0 R0 (6.625 1.75); Layer 1; Smd '55' 1.25 0.25 -0 R0 (6.625 2.25); Layer 1; Smd '56' 1.25 0.25 -0 R0 (6.625 2.75); Layer 1; Smd '57' 1.25 0.25 -0 R0 (6.625 3.25); Layer 1; Smd '58' 1.25 0.25 -0 R0 (6.625 3.75); Layer 1; Smd '59' 1.25 0.25 -0 R0 (6.625 4.25); Layer 1; Smd '60' 1.25 0.25 -0 R0 (6.625 4.75); Layer 1; Smd '61' 0.25 1.25 -0 R0 (4.75 6.625); Layer 1; Smd '62' 0.25 1.25 -0 R0 (4.25 6.625); Layer 1; Smd '63' 0.25 1.25 -0 R0 (3.75 6.625); Layer 1; Smd '64' 0.25 1.25 -0 R0 (3.25 6.625); Layer 1; Smd '65' 0.25 1.25 -0 R0 (2.75 6.625); Layer 1; Smd '66' 0.25 1.25 -0 R0 (2.25 6.625); Layer 1; Smd '67' 0.25 1.25 -0 R0 (1.75 6.625); Layer 1; Smd '68' 0.25 1.25 -0 R0 (1.25 6.625); Layer 1; Smd '69' 0.25 1.25 -0 R0 (0.75 6.625); Layer 1; Smd '70' 0.25 1.25 -0 R0 (0.25 6.625); Layer 1; Smd '71' 0.25 1.25 -0 R0 (-0.25 6.625); Layer 1; Smd '72' 0.25 1.25 -0 R0 (-0.75 6.625); Layer 1; Smd '73' 0.25 1.25 -0 R0 (-1.25 6.625); Layer 1; Smd '74' 0.25 1.25 -0 R0 (-1.75 6.625); Layer 1; Smd '75' 0.25 1.25 -0 R0 (-2.25 6.625); Layer 1; Smd '76' 0.25 1.25 -0 R0 (-2.75 6.625); Layer 1; Smd '77' 0.25 1.25 -0 R0 (-3.25 6.625); Layer 1; Smd '78' 0.25 1.25 -0 R0 (-3.75 6.625); Layer 1; Smd '79' 0.25 1.25 -0 R0 (-4.25 6.625); Layer 1; Smd '80' 0.25 1.25 -0 R0 (-4.75 6.625); Layer 21; Wire 0.254 \ (-5.715 4.7625) (-4.7625 5.715) (5.715 5.715) (5.715 -5.715) \ (-5.715 -5.715) (-5.715 4.7625); Layer 21; Change Spacing 1.27; Change Pour Solid; Change Rank 0; Polygon 0.2032 (-7.62 4.7625) (-8.255 5.08) (-8.255 4.445) (-7.62 4.7625); Layer 21; Circle 0 (-5.08 4.445) (-4.7625 4.445); Layer 21; Change Size 1.27; Change Ratio 16; Text '>NAME' R180 (-5.08 6.6675); Layer 21; Change Size 1.27; Change Ratio 16; Text '>VALUE' R0 (-5.3975 -4.445); Layer 21; Change Size 1.905; Change Ratio 13; Text '>NAME' R0 (-1.905 -0.9525); Edit TQFP-64-TSOCK.pac; Description '64 pin TQFP (PT suffix), space for transition socket'; Layer 1; Smd '1' 1.25 0.25 -0 R0 (-5.625 3.75); Layer 1; Smd '2' 1.25 0.25 -0 R0 (-5.625 3.25); Layer 1; Smd '3' 1.25 0.25 -0 R0 (-5.625 2.75); Layer 1; Smd '4' 1.25 0.25 -0 R0 (-5.625 2.25); Layer 1; Smd '5' 1.25 0.25 -0 R0 (-5.625 1.75); Layer 1; Smd '6' 1.25 0.25 -0 R0 (-5.625 1.25); Layer 1; Smd '7' 1.25 0.25 -0 R0 (-5.625 0.75); Layer 1; Smd '8' 1.25 0.25 -0 R0 (-5.625 0.25); Layer 1; Smd '9' 1.25 0.25 -0 R0 (-5.625 -0.25); Layer 1; Smd '10' 1.25 0.25 -0 R0 (-5.625 -0.75); Layer 1; Smd '11' 1.25 0.25 -0 R0 (-5.625 -1.25); Layer 1; Smd '12' 1.25 0.25 -0 R0 (-5.625 -1.75); Layer 1; Smd '13' 1.25 0.25 -0 R0 (-5.625 -2.25); Layer 1; Smd '14' 1.25 0.25 -0 R0 (-5.625 -2.75); Layer 1; Smd '15' 1.25 0.25 -0 R0 (-5.625 -3.25); Layer 1; Smd '16' 1.25 0.25 -0 R0 (-5.625 -3.75); Layer 1; Smd '17' 0.25 1.25 -0 R0 (-3.75 -5.625); Layer 1; Smd '18' 0.25 1.25 -0 R0 (-3.25 -5.625); Layer 1; Smd '19' 0.25 1.25 -0 R0 (-2.75 -5.625); Layer 1; Smd '20' 0.25 1.25 -0 R0 (-2.25 -5.625); Layer 1; Smd '21' 0.25 1.25 -0 R0 (-1.75 -5.625); Layer 1; Smd '22' 0.25 1.25 -0 R0 (-1.25 -5.625); Layer 1; Smd '23' 0.25 1.25 -0 R0 (-0.75 -5.625); Layer 1; Smd '24' 0.25 1.25 -0 R0 (-0.25 -5.625); Layer 1; Smd '25' 0.25 1.25 -0 R0 (0.25 -5.625); Layer 1; Smd '26' 0.25 1.25 -0 R0 (0.75 -5.625); Layer 1; Smd '27' 0.25 1.25 -0 R0 (1.25 -5.625); Layer 1; Smd '28' 0.25 1.25 -0 R0 (1.75 -5.625); Layer 1; Smd '29' 0.25 1.25 -0 R0 (2.25 -5.625); Layer 1; Smd '30' 0.25 1.25 -0 R0 (2.75 -5.625); Layer 1; Smd '31' 0.25 1.25 -0 R0 (3.25 -5.625); Layer 1; Smd '32' 0.25 1.25 -0 R0 (3.75 -5.625); Layer 1; Smd '33' 1.25 0.25 -0 R0 (5.625 -3.75); Layer 1; Smd '34' 1.25 0.25 -0 R0 (5.625 -3.25); Layer 1; Smd '35' 1.25 0.25 -0 R0 (5.625 -2.75); Layer 1; Smd '36' 1.25 0.25 -0 R0 (5.625 -2.25); Layer 1; Smd '37' 1.25 0.25 -0 R0 (5.625 -1.75); Layer 1; Smd '38' 1.25 0.25 -0 R0 (5.625 -1.25); Layer 1; Smd '39' 1.25 0.25 -0 R0 (5.625 -0.75); Layer 1; Smd '40' 1.25 0.25 -0 R0 (5.625 -0.25); Layer 1; Smd '41' 1.25 0.25 -0 R0 (5.625 0.25); Layer 1; Smd '42' 1.25 0.25 -0 R0 (5.625 0.75); Layer 1; Smd '43' 1.25 0.25 -0 R0 (5.625 1.25); Layer 1; Smd '44' 1.25 0.25 -0 R0 (5.625 1.75); Layer 1; Smd '45' 1.25 0.25 -0 R0 (5.625 2.25); Layer 1; Smd '46' 1.25 0.25 -0 R0 (5.625 2.75); Layer 1; Smd '47' 1.25 0.25 -0 R0 (5.625 3.25); Layer 1; Smd '48' 1.25 0.25 -0 R0 (5.625 3.75); Layer 1; Smd '49' 0.25 1.25 -0 R0 (3.75 5.625); Layer 1; Smd '50' 0.25 1.25 -0 R0 (3.25 5.625); Layer 1; Smd '51' 0.25 1.25 -0 R0 (2.75 5.625); Layer 1; Smd '52' 0.25 1.25 -0 R0 (2.25 5.625); Layer 1; Smd '53' 0.25 1.25 -0 R0 (1.75 5.625); Layer 1; Smd '54' 0.25 1.25 -0 R0 (1.25 5.625); Layer 1; Smd '55' 0.25 1.25 -0 R0 (0.75 5.625); Layer 1; Smd '56' 0.25 1.25 -0 R0 (0.25 5.625); Layer 1; Smd '57' 0.25 1.25 -0 R0 (-0.25 5.625); Layer 1; Smd '58' 0.25 1.25 -0 R0 (-0.75 5.625); Layer 1; Smd '59' 0.25 1.25 -0 R0 (-1.25 5.625); Layer 1; Smd '60' 0.25 1.25 -0 R0 (-1.75 5.625); Layer 1; Smd '61' 0.25 1.25 -0 R0 (-2.25 5.625); Layer 1; Smd '62' 0.25 1.25 -0 R0 (-2.75 5.625); Layer 1; Smd '63' 0.25 1.25 -0 R0 (-3.25 5.625); Layer 1; Smd '64' 0.25 1.25 -0 R0 (-3.75 5.625); Layer 21; Wire 0.254 \ (-4.7625 3.81) (-3.81 4.7625) (4.7625 4.7625) (4.7625 -4.7625) \ (-4.7625 -4.7625) (-4.7625 3.81); Layer 21; Change Spacing 1.27; Change Pour Solid; Change Rank 0; Polygon 0.2032 (-6.6675 3.81) (-7.3025 4.1275) (-7.3025 3.4925) (-6.6675 3.81); Layer 21; Change Size 1.27; Change Ratio 16; Text '>NAME' R180 (-4.1275 5.715); Layer 21; Change Size 1.905; Change Ratio 13; Text '>NAME' R0 (-2.8575 -0.9525); Layer 21; Circle 0 (-4.1275 3.4925) (-3.81 3.4925); Layer 21; Wire 0.2032 \ (-16.002 -16.002) (16.002 -16.002) (16.002 16.002) (-16.002 16.002) \ (-16.002 -16.002); Edit TQFP-80-14.pac; Description '80 pin TQFP 14x14mm (PF suffix)'; Layer 1; Smd '1' 1.5 0.325 -0 R0 (-7.75 6.175); Layer 1; Smd '2' 1.5 0.325 -0 R0 (-7.75 5.525); Layer 1; Smd '3' 1.5 0.325 -0 R0 (-7.75 4.875); Layer 1; Smd '4' 1.5 0.325 -0 R0 (-7.75 4.225); Layer 1; Smd '5' 1.5 0.325 -0 R0 (-7.75 3.575); Layer 1; Smd '6' 1.5 0.325 -0 R0 (-7.75 2.925); Layer 1; Smd '7' 1.5 0.325 -0 R0 (-7.75 2.275); Layer 1; Smd '8' 1.5 0.325 -0 R0 (-7.75 1.625); Layer 1; Smd '9' 1.5 0.325 -0 R0 (-7.75 0.975); Layer 1; Smd '10' 1.5 0.325 -0 R0 (-7.75 0.325); Layer 1; Smd '11' 1.5 0.325 -0 R0 (-7.75 -0.325); Layer 1; Smd '12' 1.5 0.325 -0 R0 (-7.75 -0.975); Layer 1; Smd '13' 1.5 0.325 -0 R0 (-7.75 -1.625); Layer 1; Smd '14' 1.5 0.325 -0 R0 (-7.75 -2.275); Layer 1; Smd '15' 1.5 0.325 -0 R0 (-7.75 -2.925); Layer 1; Smd '16' 1.5 0.325 -0 R0 (-7.75 -3.575); Layer 1; Smd '17' 1.5 0.325 -0 R0 (-7.75 -4.225); Layer 1; Smd '18' 1.5 0.325 -0 R0 (-7.75 -4.875); Layer 1; Smd '19' 1.5 0.325 -0 R0 (-7.75 -5.525); Layer 1; Smd '20' 1.5 0.325 -0 R0 (-7.75 -6.175); Layer 1; Smd '21' 0.325 1.5 -0 R0 (-6.175 -7.75); Layer 1; Smd '22' 0.325 1.5 -0 R0 (-5.5246 -7.75); Layer 1; Smd '23' 0.325 1.5 -0 R0 (-4.8742 -7.75); Layer 1; Smd '24' 0.325 1.5 -0 R0 (-4.2238 -7.75); Layer 1; Smd '25' 0.325 1.5 -0 R0 (-3.5734 -7.75); Layer 1; Smd '26' 0.325 1.5 -0 R0 (-2.923 -7.75); Layer 1; Smd '27' 0.325 1.5 -0 R0 (-2.2726 -7.75); Layer 1; Smd '28' 0.325 1.5 -0 R0 (-1.6222 -7.75); Layer 1; Smd '29' 0.325 1.5 -0 R0 (-0.9718 -7.75); Layer 1; Smd '30' 0.325 1.5 -0 R0 (-0.3214 -7.75); Layer 1; Smd '31' 0.325 1.5 -0 R0 (0.329 -7.75); Layer 1; Smd '32' 0.325 1.5 -0 R0 (0.9794 -7.75); Layer 1; Smd '33' 0.325 1.5 -0 R0 (1.6298 -7.75); Layer 1; Smd '34' 0.325 1.5 -0 R0 (2.2802 -7.75); Layer 1; Smd '35' 0.325 1.5 -0 R0 (2.9306 -7.75); Layer 1; Smd '36' 0.325 1.5 -0 R0 (3.581 -7.75); Layer 1; Smd '37' 0.325 1.5 -0 R0 (4.2314 -7.75); Layer 1; Smd '38' 0.325 1.5 -0 R0 (4.8818 -7.75); Layer 1; Smd '39' 0.325 1.5 -0 R0 (5.5322 -7.75); Layer 1; Smd '40' 0.325 1.5 -0 R0 (6.1826 -7.75); Layer 1; Smd '41' 1.5 0.325 -0 R0 (7.75 -6.175); Layer 1; Smd '42' 1.5 0.325 -0 R0 (7.75 -5.5246); Layer 1; Smd '43' 1.5 0.325 -0 R0 (7.75 -4.8742); Layer 1; Smd '44' 1.5 0.325 -0 R0 (7.75 -4.2238); Layer 1; Smd '45' 1.5 0.325 -0 R0 (7.75 -3.5734); Layer 1; Smd '46' 1.5 0.325 -0 R0 (7.75 -2.923); Layer 1; Smd '47' 1.5 0.325 -0 R0 (7.75 -2.2726); Layer 1; Smd '48' 1.5 0.325 -0 R0 (7.75 -1.6222); Layer 1; Smd '49' 1.5 0.325 -0 R0 (7.75 -0.9718); Layer 1; Smd '50' 1.5 0.325 -0 R0 (7.75 -0.3214); Layer 1; Smd '51' 1.5 0.325 -0 R0 (7.75 0.329); Layer 1; Smd '52' 1.5 0.325 -0 R0 (7.75 0.9794); Layer 1; Smd '53' 1.5 0.325 -0 R0 (7.75 1.6298); Layer 1; Smd '54' 1.5 0.325 -0 R0 (7.75 2.2802); Layer 1; Smd '55' 1.5 0.325 -0 R0 (7.75 2.9306); Layer 1; Smd '56' 1.5 0.325 -0 R0 (7.75 3.581); Layer 1; Smd '57' 1.5 0.325 -0 R0 (7.75 4.2314); Layer 1; Smd '58' 1.5 0.325 -0 R0 (7.75 4.8818); Layer 1; Smd '59' 1.5 0.325 -0 R0 (7.75 5.5322); Layer 1; Smd '60' 1.5 0.325 -0 R0 (7.75 6.1826); Layer 1; Smd '61' 0.325 1.5 -0 R0 (6.175 7.75); Layer 1; Smd '62' 0.325 1.5 -0 R0 (5.5246 7.75); Layer 1; Smd '63' 0.325 1.5 -0 R0 (4.8742 7.75); Layer 1; Smd '64' 0.325 1.5 -0 R0 (4.2238 7.75); Layer 1; Smd '65' 0.325 1.5 -0 R0 (3.5734 7.75); Layer 1; Smd '66' 0.325 1.5 -0 R0 (2.923 7.75); Layer 1; Smd '67' 0.325 1.5 -0 R0 (2.2726 7.75); Layer 1; Smd '68' 0.325 1.5 -0 R0 (1.6222 7.75); Layer 1; Smd '69' 0.325 1.5 -0 R0 (0.9718 7.75); Layer 1; Smd '70' 0.325 1.5 -0 R0 (0.3214 7.75); Layer 1; Smd '71' 0.325 1.5 -0 R0 (-0.329 7.75); Layer 1; Smd '72' 0.325 1.5 -0 R0 (-0.9794 7.75); Layer 1; Smd '73' 0.325 1.5 -0 R0 (-1.6298 7.75); Layer 1; Smd '74' 0.325 1.5 -0 R0 (-2.2802 7.75); Layer 1; Smd '75' 0.325 1.5 -0 R0 (-2.9306 7.75); Layer 1; Smd '76' 0.325 1.5 -0 R0 (-3.581 7.75); Layer 1; Smd '77' 0.325 1.5 -0 R0 (-4.2314 7.75); Layer 1; Smd '78' 0.325 1.5 -0 R0 (-4.8818 7.75); Layer 1; Smd '79' 0.325 1.5 -0 R0 (-5.5322 7.75); Layer 1; Smd '80' 0.325 1.5 -0 R0 (-6.1826 7.75); Layer 21; Wire 0.254 (6.6675 6.6675) (6.6675 -6.6675) (-6.6675 -6.6675) (-6.6675 6.0325) \ (-6.0325 6.6675) (6.6675 6.6675); Layer 21; Circle 0 (-6.0325 5.715) (-5.715 5.715); Layer 21; Change Spacing 1.27; Change Pour Solid; Change Rank 0; Polygon 0.2032 (-8.89 6.35) (-9.525 6.6675) (-9.525 6.0325) (-8.89 6.35); Layer 21; Change Size 1.27; Change Ratio 16; Text '>NAME' R180 (-6.6675 8.255); Layer 21; Change Size 1.905; Change Ratio 13; Text '>NAME' R0 (-2.54 1.27); Layer 21; Change Size 1.27; Change Ratio 16; Text '>VALUE' R0 (-6.0325 -2.54); Edit SOT-23.pac; Description 'Standard SOT-23, 2 rows of 3 pins, .0375 pin pitch'; Layer 1; Smd '5' 1.016 0.4826 -0 R90 (0 1.27); Layer 1; Smd '2' 1.016 0.4826 -0 R90 (0 -1.27); Layer 1; Smd '6' 1.016 0.4826 -0 R90 (-0.9525 1.27); Layer 1; Smd '4' 1.016 0.4826 -0 R90 (0.9525 1.27); Layer 1; Smd '1' 1.016 0.4826 -0 R90 (-0.9525 -1.27); Layer 1; Smd '3' 1.016 0.4826 -0 R90 (0.9525 -1.27); Layer 21; Wire 0.2032 \ (1.524 0.635) (-1.524 0.635) (-1.524 -0.635) (1.524 -0.635) \ (1.524 0.635); Layer 21; Change Spacing 1.27; Change Pour Solid; Change Rank 0; Polygon 0.2032 (-1.5875 -1.5875) (-2.2225 -1.27) (-2.2225 -1.905) (-1.5875 -1.5875); Layer 25; Change Size 1.27; Change Ratio 16; Text '>NAME' R180 (-1.5875 0.635); Edit TQFP-44-10.pac; Description '44 pin TQFP 10x10mm (PT suffix}'; Layer 1; Smd '1' 2 0.4 -0 R0 (-6 4); Layer 1; Smd '2' 2 0.4 -0 R0 (-6 3.2); Layer 1; Smd '3' 2 0.4 -0 R0 (-6 2.4); Layer 1; Smd '4' 2 0.4 -0 R0 (-6 1.6); Layer 1; Smd '5' 2 0.4 -0 R0 (-6 0.8); Layer 1; Smd '6' 2 0.4 -0 R0 (-6 0); Layer 1; Smd '7' 2 0.4 -0 R0 (-6 -0.8); Layer 1; Smd '8' 2 0.4 -0 R0 (-6 -1.6); Layer 1; Smd '9' 2 0.4 -0 R0 (-6 -2.4); Layer 1; Smd '10' 2 0.4 -0 R0 (-6 -3.2); Layer 1; Smd '11' 2 0.4 -0 R0 (-6 -4); Layer 1; Smd '12' 0.4 2 -0 R0 (-4 -6); Layer 1; Smd '13' 0.4 2 -0 R0 (-3.2 -6); Layer 1; Smd '14' 0.4 2 -0 R0 (-2.4 -6); Layer 1; Smd '15' 0.4 2 -0 R0 (-1.6 -6); Layer 1; Smd '16' 0.4 2 -0 R0 (-0.8 -6); Layer 1; Smd '17' 0.4 2 -0 R0 (0 -6); Layer 1; Smd '18' 0.4 2 -0 R0 (0.8 -6); Layer 1; Smd '19' 0.4 2 -0 R0 (1.6 -6); Layer 1; Smd '20' 0.4 2 -0 R0 (2.4 -6); Layer 1; Smd '21' 0.4 2 -0 R0 (3.2 -6); Layer 1; Smd '22' 0.4 2 -0 R0 (4 -6); Layer 1; Smd '23' 2 0.4 -0 R0 (6 -4); Layer 1; Smd '24' 2 0.4 -0 R0 (6 -3.2); Layer 1; Smd '25' 2 0.4 -0 R0 (6 -2.4); Layer 1; Smd '26' 2 0.4 -0 R0 (6 -1.6); Layer 1; Smd '27' 2 0.4 -0 R0 (6 -0.8); Layer 1; Smd '28' 2 0.4 -0 R0 (6 0); Layer 1; Smd '29' 2 0.4 -0 R0 (6 0.8); Layer 1; Smd '30' 2 0.4 -0 R0 (6 1.6); Layer 1; Smd '31' 2 0.4 -0 R0 (6 2.4); Layer 1; Smd '32' 2 0.4 -0 R0 (6 3.2); Layer 1; Smd '33' 2 0.4 -0 R0 (6 4); Layer 1; Smd '34' 0.4 2 -0 R0 (4 6); Layer 1; Smd '35' 0.4 2 -0 R0 (3.2 6); Layer 1; Smd '36' 0.4 2 -0 R0 (2.4 6); Layer 1; Smd '37' 0.4 2 -0 R0 (1.6 6); Layer 1; Smd '38' 0.4 2 -0 R0 (0.8 6); Layer 1; Smd '39' 0.4 2 -0 R0 (0 6); Layer 1; Smd '40' 0.4 2 -0 R0 (-0.8 6); Layer 1; Smd '41' 0.4 2 -0 R0 (-1.6 6); Layer 1; Smd '42' 0.4 2 -0 R0 (-2.4 6); Layer 1; Smd '43' 0.4 2 -0 R0 (-3.2 6); Layer 1; Smd '44' 0.4 2 -0 R0 (-4 6); Layer 21; Wire 0.2032 \ (4.7625 4.7625) (4.7625 -4.7625) (-4.7625 -4.7625) (-4.7625 4.1275) \ (-4.1275 4.7625) (4.7625 4.7625); Layer 21; Circle 0 (-4.1275 3.81) (-3.81 3.81); Layer 21; Change Spacing 1.27; Change Pour Solid; Change Rank 0; Polygon 0.2032 (-7.3025 4.1275) (-8.255 4.445) (-8.255 3.81) (-7.3025 4.1275); Layer 25; Change Size 1.27; Change Ratio 16; Text '>NAME' R180 (-4.7625 6.0325); Layer 25; Change Size 1.905; Change Ratio 13; Text '>NAME' R0 (-2.2225 -0.9525); Edit SOIC-28.pac; Description '28 pin SOIC'; Layer 1; Smd '1' 0.635 1.016 -0 R0 (-8.255 -5.08); Layer 1; Smd '2' 0.635 1.016 -0 R0 (-6.985 -5.08); Layer 1; Smd '3' 0.635 1.016 -0 R0 (-5.715 -5.08); Layer 1; Smd '4' 0.635 1.016 -0 R0 (-4.445 -5.08); Layer 1; Smd '5' 0.635 1.016 -0 R0 (-3.175 -5.08); Layer 1; Smd '6' 0.635 1.016 -0 R0 (-1.905 -5.08); Layer 1; Smd '7' 0.635 1.016 -0 R0 (-0.635 -5.08); Layer 1; Smd '8' 0.635 1.016 -0 R0 (0.635 -5.08); Layer 1; Smd '9' 0.635 1.016 -0 R0 (1.905 -5.08); Layer 1; Smd '10' 0.635 1.016 -0 R0 (3.175 -5.08); Layer 1; Smd '11' 0.635 1.016 -0 R0 (4.445 -5.08); Layer 1; Smd '12' 0.635 1.016 -0 R0 (5.715 -5.08); Layer 1; Smd '13' 0.635 1.016 -0 R0 (6.985 -5.08); Layer 1; Smd '14' 0.635 1.016 -0 R0 (8.255 -5.08); Layer 1; Smd '15' 0.635 1.016 -0 R0 (8.255 5.08); Layer 1; Smd '16' 0.635 1.016 -0 R0 (6.985 5.08); Layer 1; Smd '17' 0.635 1.016 -0 R0 (5.715 5.08); Layer 1; Smd '18' 0.635 1.016 -0 R0 (4.445 5.08); Layer 1; Smd '19' 0.635 1.016 -0 R0 (3.175 5.08); Layer 1; Smd '20' 0.635 1.016 -0 R0 (1.905 5.08); Layer 1; Smd '21' 0.635 1.016 -0 R0 (0.635 5.08); Layer 1; Smd '22' 0.635 1.016 -0 R0 (-0.635 5.08); Layer 1; Smd '23' 0.635 1.016 -0 R0 (-1.905 5.08); Layer 1; Smd '24' 0.635 1.016 -0 R0 (-3.175 5.08); Layer 1; Smd '25' 0.635 1.016 -0 R0 (-4.445 5.08); Layer 1; Smd '26' 0.635 1.016 -0 R0 (-5.715 5.08); Layer 1; Smd '27' 0.635 1.016 -0 R0 (-6.985 5.08); Layer 1; Smd '28' 0.635 1.016 -0 R0 (-8.255 5.08); Layer 21; Wire 0.2032 \ (8.89 -4.318) (8.89 4.318) (-8.89 4.318) (-8.89 0.9525); Wire 0.2032 (-8.89 -0.9525) (-8.89 -4.318) (8.89 -4.318); Layer 21; Change Spacing 1.27; Change Pour Solid; Change Rank 0; Polygon 0.2032 (-8.89 -5.08) (-9.652 -4.572) (-9.652 -5.588) (-8.89 -5.08); Layer 25; Change Size 1.27; Change Ratio 16; Text '>NAME' R90 (-9.2075 -1.905); Layer 25; Change Size 1.905; Change Ratio 13; Text '>NAME' R0 (-2.8575 0.635); Layer 21; Wire 0.2032 \ (-8.89 0.9525) -180 (-8.89 -0.9525); Layer 21; Circle 0 (-8.255 -3.81) (-7.9375 -3.81); Edit PIC16C773.dev; Prefix ''; Description '\ PIC 16C773, 28 pin, 4K prog, 6x 12-bit A/D, USART, MSSP, 2 CCP,\n\ timer 0-2, 256 RAM'; Value Off; Add 16C773 'G$1' Next 0 (0 0); Package 'PDIP-28' '-SP'; Technology ''; Connect 'G$1.MCLR-' '1' 'G$1.RA0/AN0' '2' 'G$1.RA1/AN1' '3' 'G$1.RA2/AN2/VREF-' '4' 'G$1.RA3/AN3/VREF+' '5' \ 'G$1.RA4/T0CKIN' '6' 'G$1.AVDD' '7' 'G$1.AVSS' '8' 'G$1.OSC1/CLKIN' '9' 'G$1.OSC2/CLKOUT' '10' 'G$1.RC0/T1OSO/T1CKIN' '11' \ 'G$1.RC1/T1OSI/CCP2' '12' 'G$1.RC2/CCP1' '13' 'G$1.RC3/SCK/SCL' '14' 'G$1.RC4/SDI/SDA' '15' 'G$1.RC5/SD0' '16' 'G$1.RC6/TX/CK' '17' \ 'G$1.RC7/RX/DT' '18' 'G$1.VSS' '19' 'G$1.VDD' '20' 'G$1.RB0/INT' '21' 'G$1.RB1/SS-' '22' 'G$1.RB2/AN8' '23' \ 'G$1.RB3/AN9/LVPGM' '24' 'G$1.RB4' '25' 'G$1.RB5' '26' 'G$1.RB6/PGC' '27' 'G$1.RB7/PGD' '28'; Edit PIC16F876-?.dev; Prefix 'IC'; Description '\ PIC 16F876, 28 pin, 8K prog, 256 EEPROM, USART, MSSP, 2 CCP,\n\ timer 0-2, 5x 10-bit A/D, 368 RAM'; Value Off; Add 16F876 'G$1' Next 0 (0 0); Package 'PDIP-28' 'SP'; Technology ''; Connect 'G$1.MCLR-' '1' 'G$1.RA0/AN0' '2' 'G$1.RA1/AN1' '3' 'G$1.RA2/AN2/VREF-' '4' 'G$1.RA3/AN3/VREF+' '5' \ 'G$1.RA4/T0CKIN' '6' 'G$1.RA5/AN4/SS-' '7' 'G$1.VSS1' '8' 'G$1.OSC1/CLKIN' '9' 'G$1.OSC2/CLKOUT' '10' 'G$1.RC0/T1OSO/T1CKIN' '11' \ 'G$1.RC1/T1OSI/CCP2' '12' 'G$1.RC2/CCP1' '13' 'G$1.RC3/SCK/SCL' '14' 'G$1.RC4/SDI/SDA' '15' 'G$1.RC5/SD0' '16' 'G$1.RC6/TX/CK' '17' \ 'G$1.RC7/RX/DT' '18' 'G$1.VSS2' '19' 'G$1.VDD' '20' 'G$1.RB0/INT' '21' 'G$1.RB1' '22' 'G$1.RB2' '23' \ 'G$1.RB3/LVPGM' '24' 'G$1.RB4' '25' 'G$1.RB5' '26' 'G$1.RB6/PGC' '27' 'G$1.RB7/PGD' '28'; Edit PIC16F877-?.dev; Prefix 'IC'; Description 'PIC 16F877, 40 pin, 8K prog, 256 EEPROM, USART, MSSP, 2 CCP, timer 0-2, 8x 10 bit A/D, 368 RAM'; Value Off; Add 16F877 'G$1' Next 1 (0 0); Package 'DIP-40' 'P'; Technology ''; Connect 'G$1.MCLR-' '1' 'G$1.RA0/AN0' '2' 'G$1.RA1/AN1' '3' 'G$1.RA2/AN2/VREF-' '4' 'G$1.RA3/AN3/VREF+' '5' \ 'G$1.RA4/T0CKIN' '6' 'G$1.RA5/AN4/SS-' '7' 'G$1.RE0/RD/AN5' '8' 'G$1.RE1/WR/AN6' '9' 'G$1.RE2/CS/AN7' '10' 'G$1.VDD1' '11' \ 'G$1.VSS1' '12' 'G$1.OSC1/CLKIN' '13' 'G$1.OSC2/CLKOUT' '14' 'G$1.RC0/T1OSO/T1CKIN' '15' 'G$1.RC1/T1OSI/CCP2' '16' 'G$1.RC2/CCP1' '17' \ 'G$1.RC3/SCK/SCL' '18' 'G$1.RD0' '19' 'G$1.RD1' '20' 'G$1.RD2' '21' 'G$1.RD3' '22' 'G$1.RC4/SDI/SDA' '23' \ 'G$1.RC5/SD0' '24' 'G$1.RC6/TX/CK' '25' 'G$1.RC7/RX/DT' '26' 'G$1.RD4' '27' 'G$1.RD5' '28' 'G$1.RD6' '29' \ 'G$1.RD7' '30' 'G$1.VSS2' '31' 'G$1.VDD2' '32' 'G$1.RB0/INT' '33' 'G$1.RB1' '34' 'G$1.RB2' '35' \ 'G$1.RB3/LVPGM' '36' 'G$1.RB4' '37' 'G$1.RB5' '38' 'G$1.RB6/PGC' '39' 'G$1.RB7/PGD' '40'; Edit PIC16C622A-?.dev; Prefix 'IC'; Description '18/20 pin, 2K prog, 2 comp, 128 RAM'; Value Off; Add 16C622 'G$1' Next 0 (0 0); Package 'DIP-18' 'P'; Technology ''; Connect 'G$1.RA2/AN2/VREF' '1' 'G$1.RA3/AN3' '2' 'G$1.RA4/T0CKIN' '3' 'G$1.MCLR-' '4' 'G$1.VSS' '5' \ 'G$1.RB0/INT' '6' 'G$1.RB1' '7' 'G$1.RB2' '8' 'G$1.RB3' '9' 'G$1.RB4' '10' 'G$1.RB5' '11' \ 'G$1.RB6' '12' 'G$1.RB7' '13' 'G$1.VDD' '14' 'G$1.OSC2/CLKOUT' '15' 'G$1.OSC1/CLKIN' '16' 'G$1.RA0/AN0' '17' \ 'G$1.RA1/AN1' '18'; Edit PIC16*F628-?.dev; Prefix 'IC'; Description '18/20 pins, 2K prog, 128 EEPROM, 2 comp, 1 CCP, 224 RAM'; Value Off; Add 16F628 'G$1' Next 0 (0 0); Package 'DIP-18' 'P'; Technology '' 'L'; Connect 'G$1.RA2/AN2/VREF' '1' 'G$1.RA3/AN3/CMP1' '2' 'G$1.RA4/T0CKIN/CMP2' '3' 'G$1.RA5/MCLR/THV' '4' 'G$1.VSS' '5' \ 'G$1.RB0/INT' '6' 'G$1.RB1/RX/DT' '7' 'G$1.RB2/TX/CK' '8' 'G$1.RB3/CCP1' '9' 'G$1.RB4/PGM' '10' 'G$1.RB5' '11' \ 'G$1.RB6/T1OSO/T1CLK' '12' 'G$1.RB7/T1OSI' '13' 'G$1.VDD' '14' 'G$1.RA6/OSC2/CLKOUT' '15' 'G$1.RA7/OSC1/CLKIN' '16' 'G$1.RA0/AN0' '17' \ 'G$1.RA1/AN1' '18'; Edit PIC12F629-?.dev; Prefix 'IC'; Description '8 pins, 1K prog, 128 EEPROM, 1 comp'; Value Off; Add 12F629 'G$1' Next 0 (0 0); Package 'DIP-8' 'P'; Technology ''; Connect 'G$1.VDD' '1' 'G$1.GP5/T1CKI/OSC1/CLKIN' '2' 'G$1.GP4/T1G/OSC2/CLKOUT' '3' 'G$1.GP3/MCLR' '4' 'G$1.GP2/T0CKI/INT/COUT' '5' \ 'G$1.GP1/CIN-' '6' 'G$1.GP0/CIN+' '7' 'G$1.VSS' '8'; Edit PIC12F675-?.dev; Prefix 'IC'; Description '8 pins, 1K prog, 128 EEPROM, 1 comp, A/D'; Value Off; Add 12F675 'G$1' Next 0 (0 0); Package 'DIP-8' 'P'; Technology ''; Connect 'G$1.VDD' '1' 'G$1.GP5/T1CKI/OSC1/CLKIN' '2' 'G$1.GP4/T1G/OSC2/CLKOUT' '3' 'G$1.GP3/MCLR' '4' 'G$1.GP2/AN2/T0CKI/INT/COUT' '5' \ 'G$1.GP1/AN1/CIN-' '6' 'G$1.GP0/AN0/CIN+' '7' 'G$1.VSS' '8'; Edit PIC18F452-?.dev; Prefix 'IC'; Description '\ 18F452, 40 pin, 32Kb prog, 1536b data, 256 EEPROM
\n\ USART, MSSP, 2 CCP, 8x 10 bit A/D'; Value Off; Add 18F4X2 'G$1' Next 0 (0 0); Package 'DIP-40' 'P'; Technology ''; Connect 'G$1.MCLR/VPP' '1' 'G$1.RA0/AN0' '2' 'G$1.RA1/AN1' '3' 'G$1.RA2/AN2/VREF-' '4' 'G$1.RA3/AN3/VREF+' '5' \ 'G$1.RA4/T0CKIN' '6' 'G$1.RA5/AN4/SS/LVIN' '7' 'G$1.RE0/RD/AN5' '8' 'G$1.RE1/WR/AN6' '9' 'G$1.RE2/CS/AN7' '10' 'G$1.VDD1' '11' \ 'G$1.VSS1' '12' 'G$1.OSC1/CKIN' '13' 'G$1.OSC2/CKOUT/RA6' '14' 'G$1.RC0/T1OSO/T1CKIN' '15' 'G$1.RC1/T1OSI/CCP2' '16' 'G$1.RC2/CCP1' '17' \ 'G$1.RC3/SCK/SCL' '18' 'G$1.RD0' '19' 'G$1.RD1' '20' 'G$1.RD2' '21' 'G$1.RD3' '22' 'G$1.RC4/SDI/SDA' '23' \ 'G$1.RC5/SDO' '24' 'G$1.RC6/TX/UCK' '25' 'G$1.RC7/RX/UDT' '26' 'G$1.RD4' '27' 'G$1.RD5' '28' 'G$1.RD6' '29' \ 'G$1.RD7' '30' 'G$1.VSS2' '31' 'G$1.VDD2' '32' 'G$1.RB0/INT0' '33' 'G$1.RB1/INT1' '34' 'G$1.RB2/INT2' '35' \ 'G$1.RB3/CCP2' '36' 'G$1.RB4' '37' 'G$1.RB5/PGM' '38' 'G$1.RB6/PGC' '39' 'G$1.RB7/PGD' '40'; Edit PIC18*F1320-?.dev; Prefix 'IC'; Description '18/20 pins, 4K prog, 256 EEPROM, 7 A/D, USART, CCP, 256 RAM'; Value Off; Add 18F1320 'G$1' Next 0 (0 0); Package 'DIP-18' 'I/P'; Technology '' 'L'; Connect 'G$1.RA0/AN0' '1' 'G$1.RA1/AN1/LVDIN' '2' 'G$1.RA4/T0CKIN' '3' 'G$1.RA5/MCLR/VPP' '4' 'G$1.VSS' '5' \ 'G$1.RA2/AN2/VREF-' '6' 'G$1.RA3/AN3/VREF+' '7' 'G$1.RB0/AN4/INT0' '8' 'G$1.RB1/AN5/INT1/TX/CK' '9' 'G$1.RB4/AN6/RX/DT' '10' 'G$1.RB5/LVPGM' '11' \ 'G$1.RB6/P1C/T1OSO/PGC' '12' 'G$1.RB7/P1D/T1OSI/PGD' '13' 'G$1.VDD' '14' 'G$1.RA7/OSC1/CKIN' '15' 'G$1.RA6/OSC2/CKOUT' '16' 'G$1.RB2/INT2/PIB' '17' \ 'G$1.RB3/CCP1/PIA' '18'; Package 'DIP-18' 'E/P'; Technology '' 'L'; Connect 'G$1.RA0/AN0' '1' 'G$1.RA1/AN1/LVDIN' '2' 'G$1.RA4/T0CKIN' '3' 'G$1.RA5/MCLR/VPP' '4' 'G$1.VSS' '5' \ 'G$1.RA2/AN2/VREF-' '6' 'G$1.RA3/AN3/VREF+' '7' 'G$1.RB0/AN4/INT0' '8' 'G$1.RB1/AN5/INT1/TX/CK' '9' 'G$1.RB4/AN6/RX/DT' '10' 'G$1.RB5/LVPGM' '11' \ 'G$1.RB6/P1C/T1OSO/PGC' '12' 'G$1.RB7/P1D/T1OSI/PGD' '13' 'G$1.VDD' '14' 'G$1.RA7/OSC1/CKIN' '15' 'G$1.RA6/OSC2/CKOUT' '16' 'G$1.RB2/INT2/PIB' '17' \ 'G$1.RB3/CCP1/PIA' '18'; Edit PIC18*F252-?.dev; Prefix 'IC'; Description '18F252, 28 pin, 32Kb prog, 1536 data, 256 EEPROM'; Value Off; Add 18F252 'G$1' Next 0 (0 0); Package 'PDIP-28' 'I/P'; Technology '' 'L'; Connect 'G$1.MCLR/VPP' '1' 'G$1.RA0/AN0' '2' 'G$1.RA1/AN1' '3' 'G$1.RA2/AN2/VREF-' '4' 'G$1.RA3/AN3/VREF+' '5' \ 'G$1.RA4/T0CKIN' '6' 'G$1.RA5/AN4/SS/LVDIN' '7' 'G$1.VSS1' '8' 'G$1.OSC1/CLKIN' '9' 'G$1.OSC2/CLKOUT/RA6' '10' 'G$1.RC0/T1OSO/T1CKIN' '11' \ 'G$1.RC1/T1OSI/CCP2A' '12' 'G$1.RC2/CCP1' '13' 'G$1.RC3/SCK/SCL' '14' 'G$1.RC4/SDI/SDA' '15' 'G$1.RC5/SD0' '16' 'G$1.RC6/TX/CK' '17' \ 'G$1.RC7/RX/DT' '18' 'G$1.VSS2' '19' 'G$1.VDD' '20' 'G$1.RB0/INT0' '21' 'G$1.RB1/INT1' '22' 'G$1.RB2/INT2' '23' \ 'G$1.RB3/CCP2B' '24' 'G$1.RB4' '25' 'G$1.RB5/LVPGM' '26' 'G$1.RB6/PGC' '27' 'G$1.RB7/PGD' '28'; Package 'PDIP-28' 'E/P'; Technology '' 'L'; Connect 'G$1.MCLR/VPP' '1' 'G$1.RA0/AN0' '2' 'G$1.RA1/AN1' '3' 'G$1.RA2/AN2/VREF-' '4' 'G$1.RA3/AN3/VREF+' '5' \ 'G$1.RA4/T0CKIN' '6' 'G$1.RA5/AN4/SS/LVDIN' '7' 'G$1.VSS1' '8' 'G$1.OSC1/CLKIN' '9' 'G$1.OSC2/CLKOUT/RA6' '10' 'G$1.RC0/T1OSO/T1CKIN' '11' \ 'G$1.RC1/T1OSI/CCP2A' '12' 'G$1.RC2/CCP1' '13' 'G$1.RC3/SCK/SCL' '14' 'G$1.RC4/SDI/SDA' '15' 'G$1.RC5/SD0' '16' 'G$1.RC6/TX/CK' '17' \ 'G$1.RC7/RX/DT' '18' 'G$1.VSS2' '19' 'G$1.VDD' '20' 'G$1.RB0/INT0' '21' 'G$1.RB1/INT1' '22' 'G$1.RB2/INT2' '23' \ 'G$1.RB3/CCP2B' '24' 'G$1.RB4' '25' 'G$1.RB5/LVPGM' '26' 'G$1.RB6/PGC' '27' 'G$1.RB7/PGD' '28'; Package 'SOIC-28' 'I/SO'; Technology '' 'L'; Connect 'G$1.MCLR/VPP' '1' 'G$1.RA0/AN0' '2' 'G$1.RA1/AN1' '3' 'G$1.RA2/AN2/VREF-' '4' 'G$1.RA3/AN3/VREF+' '5' \ 'G$1.RA4/T0CKIN' '6' 'G$1.RA5/AN4/SS/LVDIN' '7' 'G$1.VSS1' '8' 'G$1.OSC1/CLKIN' '9' 'G$1.OSC2/CLKOUT/RA6' '10' 'G$1.RC0/T1OSO/T1CKIN' '11' \ 'G$1.RC1/T1OSI/CCP2A' '12' 'G$1.RC2/CCP1' '13' 'G$1.RC3/SCK/SCL' '14' 'G$1.RC4/SDI/SDA' '15' 'G$1.RC5/SD0' '16' 'G$1.RC6/TX/CK' '17' \ 'G$1.RC7/RX/DT' '18' 'G$1.VSS2' '19' 'G$1.VDD' '20' 'G$1.RB0/INT0' '21' 'G$1.RB1/INT1' '22' 'G$1.RB2/INT2' '23' \ 'G$1.RB3/CCP2B' '24' 'G$1.RB4' '25' 'G$1.RB5/LVPGM' '26' 'G$1.RB6/PGC' '27' 'G$1.RB7/PGD' '28'; Package 'SOIC-28' 'E/SO'; Technology '' 'L'; Connect 'G$1.MCLR/VPP' '1' 'G$1.RA0/AN0' '2' 'G$1.RA1/AN1' '3' 'G$1.RA2/AN2/VREF-' '4' 'G$1.RA3/AN3/VREF+' '5' \ 'G$1.RA4/T0CKIN' '6' 'G$1.RA5/AN4/SS/LVDIN' '7' 'G$1.VSS1' '8' 'G$1.OSC1/CLKIN' '9' 'G$1.OSC2/CLKOUT/RA6' '10' 'G$1.RC0/T1OSO/T1CKIN' '11' \ 'G$1.RC1/T1OSI/CCP2A' '12' 'G$1.RC2/CCP1' '13' 'G$1.RC3/SCK/SCL' '14' 'G$1.RC4/SDI/SDA' '15' 'G$1.RC5/SD0' '16' 'G$1.RC6/TX/CK' '17' \ 'G$1.RC7/RX/DT' '18' 'G$1.VSS2' '19' 'G$1.VDD' '20' 'G$1.RB0/INT0' '21' 'G$1.RB1/INT1' '22' 'G$1.RB2/INT2' '23' \ 'G$1.RB3/CCP2B' '24' 'G$1.RB4' '25' 'G$1.RB5/LVPGM' '26' 'G$1.RB6/PGC' '27' 'G$1.RB7/PGD' '28'; Edit PIC16F630-?.dev; Prefix 'IC'; Description '14 pins, 1K prog, 128 EEPROM, comp, 64 RAM'; Value Off; Add 16F630 'G$1' Next 0 (0 0); Package 'DIP-14' 'I/P'; Technology ''; Connect 'G$1.VDD' '1' 'G$1.RA5/T1CKIN/OSCIN' '2' 'G$1.RA4/T1GATE/OSCOUT' '3' 'G$1.RA3/MCLR/VPP' '4' 'G$1.RC5' '5' \ 'G$1.RC4' '6' 'G$1.RC3' '7' 'G$1.RC2' '8' 'G$1.RC1' '9' 'G$1.RC0' '10' 'G$1.RA2/INT/COUT/T0CKIN' '11' \ 'G$1.RA1/CIN-/PGC' '12' 'G$1.RA0/CIN+/PGD' '13' 'G$1.VSS' '14'; Edit PIC30F2010.dev; Prefix 'IC'; Description 'dsPIC, 28 pin, 4K prog, 512 RAM, 1024 EEPROM, 6 chan 10 bit 500KHz A/D'; Value Off; Add 30F2010 'G$1' Next 0 (0 0); Package 'PDIP-28' '-I/SP'; Technology ''; Connect 'G$1.MCLR' '1' 'G$1.RB0,CN2' '2' 'G$1.RB1,CN3' '3' 'G$1.RB2,CN4' '4' 'G$1.RB3,CN5' '5' \ 'G$1.RB4,CN6' '6' 'G$1.RB5,CN7' '7' 'G$1.VSS1' '8' 'G$1.OSC1,CLKI' '9' 'G$1.RC15,OSC2,CLKO' '10' 'G$1.RC13,CN1' '11' \ 'G$1.RC14,CN0' '12' 'G$1.VDD1' '13' 'G$1.RD1' '14' 'G$1.RD0' '15' 'G$1.RE8' '16' 'G$1.RF3' '17' \ 'G$1.RF2' '18' 'G$1.VSS2' '19' 'G$1.VDD2' '20' 'G$1.PWM3H,RE5' '21' 'G$1.PWM3L,RE4' '22' 'G$1.PWM2H,RE3' '23' \ 'G$1.PWM2L,RE2' '24' 'G$1.PWM1H,RE1' '25' 'G$1.PWM1L,RE0' '26' 'G$1.AVSS' '27' 'G$1.AVDD' '28'; Edit PIC18*F6520-?.dev; Prefix 'IC'; Description '64 pins, 32Kb prog, 2048 data, 1K EEPROM, 12 A/D, 2 comp, 5 CCP, 2 UART, IIC, SPI'; Value Off; Add 18F6520 'G$1' Next 0 (0 0); Package 'TQFP-64' 'PT'; Technology '' 'L'; Connect 'G$1.WR,RE1' '1' 'G$1.RD,RE0' '2' 'G$1.CCP3,RG0' '3' 'G$1.TX2,CK2,RG1' '4' 'G$1.RX2,DT2,RG2' '5' \ 'G$1.CCP4,RG3' '6' 'G$1.MCLR' '7' 'G$1.CCP5,RG4' '8' 'G$1.VSS1' '9' 'G$1.VDD1' '10' 'G$1.RF7,SS' '11' \ 'G$1.RF6,AN11' '12' 'G$1.RF5,AN10,CVREF' '13' 'G$1.RF4,AN9' '14' 'G$1.RF3,AN8' '15' 'G$1.RF2,AN7,C1OUT' '16' 'G$1.RF1,AN6,C2OUT' '17' \ 'G$1.RF0,AN5' '18' 'G$1.AVDD' '19' 'G$1.AVSS' '20' 'G$1.RA3,AN3,VREF+' '21' 'G$1.RA2,AN2,VREF-' '22' 'G$1.RA1,AN1' '23' \ 'G$1.RA0,AN0' '24' 'G$1.VSS2' '25' 'G$1.VDD2' '26' 'G$1.RA5,AN4,LVDIN' '27' 'G$1.RA4,T0CKI' '28' 'G$1.T1OSI,CCP2,RC1' '29' \ 'G$1.T1OSO,T13CKI,RC0' '30' 'G$1.TX1,CK1,RC6' '31' 'G$1.RX1,DT1,RC7' '32' 'G$1.CCP1,RC2' '33' 'G$1.SCK,SCL,RC3' '34' 'G$1.SDI,SDA,RC4' '35' \ 'G$1.SDO,RC5' '36' 'G$1.PGD,RB7' '37' 'G$1.VDD3' '38' 'G$1.OSC1,CLKI' '39' 'G$1.RA6,OSC2,CLKO' '40' 'G$1.VSS3' '41' \ 'G$1.PGC,RB6' '42' 'G$1.PGM,RB5' '43' 'G$1.RB4' '44' 'G$1.INT3,CCP2,RB3' '45' 'G$1.INT2,RB2' '46' 'G$1.INT1,RB1' '47' \ 'G$1.INT0,RB0' '48' 'G$1.PSP7,RD7' '49' 'G$1.PSP6,RD6' '50' 'G$1.PSP5,RD5' '51' 'G$1.PSP4,RD4' '52' 'G$1.PSP3,RD3' '53' \ 'G$1.PSP2,RD2' '54' 'G$1.PSP1,RD1' '55' 'G$1.VSS4' '56' 'G$1.VDD4' '57' 'G$1.PSP0,RD0' '58' 'G$1.CCP2,RE7' '59' \ 'G$1.RE6' '60' 'G$1.RE5' '61' 'G$1.RE4' '62' 'G$1.RE3' '63' 'G$1.CS,RE2' '64'; Package 'TQFP-64-TSOCK' 'PT-TS'; Technology '' 'L'; Connect 'G$1.WR,RE1' '1' 'G$1.RD,RE0' '2' 'G$1.CCP3,RG0' '3' 'G$1.TX2,CK2,RG1' '4' 'G$1.RX2,DT2,RG2' '5' \ 'G$1.CCP4,RG3' '6' 'G$1.MCLR' '7' 'G$1.CCP5,RG4' '8' 'G$1.VSS1' '9' 'G$1.VDD1' '10' 'G$1.RF7,SS' '11' \ 'G$1.RF6,AN11' '12' 'G$1.RF5,AN10,CVREF' '13' 'G$1.RF4,AN9' '14' 'G$1.RF3,AN8' '15' 'G$1.RF2,AN7,C1OUT' '16' 'G$1.RF1,AN6,C2OUT' '17' \ 'G$1.RF0,AN5' '18' 'G$1.AVDD' '19' 'G$1.AVSS' '20' 'G$1.RA3,AN3,VREF+' '21' 'G$1.RA2,AN2,VREF-' '22' 'G$1.RA1,AN1' '23' \ 'G$1.RA0,AN0' '24' 'G$1.VSS2' '25' 'G$1.VDD2' '26' 'G$1.RA5,AN4,LVDIN' '27' 'G$1.RA4,T0CKI' '28' 'G$1.T1OSI,CCP2,RC1' '29' \ 'G$1.T1OSO,T13CKI,RC0' '30' 'G$1.TX1,CK1,RC6' '31' 'G$1.RX1,DT1,RC7' '32' 'G$1.CCP1,RC2' '33' 'G$1.SCK,SCL,RC3' '34' 'G$1.SDI,SDA,RC4' '35' \ 'G$1.SDO,RC5' '36' 'G$1.PGD,RB7' '37' 'G$1.VDD3' '38' 'G$1.OSC1,CLKI' '39' 'G$1.RA6,OSC2,CLKO' '40' 'G$1.VSS3' '41' \ 'G$1.PGC,RB6' '42' 'G$1.PGM,RB5' '43' 'G$1.RB4' '44' 'G$1.INT3,CCP2,RB3' '45' 'G$1.INT2,RB2' '46' 'G$1.INT1,RB1' '47' \ 'G$1.INT0,RB0' '48' 'G$1.PSP7,RD7' '49' 'G$1.PSP6,RD6' '50' 'G$1.PSP5,RD5' '51' 'G$1.PSP4,RD4' '52' 'G$1.PSP3,RD3' '53' \ 'G$1.PSP2,RD2' '54' 'G$1.PSP1,RD1' '55' 'G$1.VSS4' '56' 'G$1.VDD4' '57' 'G$1.PSP0,RD0' '58' 'G$1.CCP2,RE7' '59' \ 'G$1.RE6' '60' 'G$1.RE5' '61' 'G$1.RE4' '62' 'G$1.RE3' '63' 'G$1.CS,RE2' '64'; Edit PIC30F6010-?.dev; Prefix 'IC'; Description '\ dsPIC, 80 pin, 48Kw prog, 8Kb RAM, 4Kb EEPROM, 16 A/D, 8 MPWM, 2 UART
\n\ 2 CAN, 1 IIC, 2 SPI, 8 PWM, 8 capture'; Value Off; Add 30F6010 'G$1' Next 0 (0 0); Package 'TQFP-80-12' 'PT'; Technology ''; Connect 'G$1.RE5,PWM3H' '1' 'G$1.RE6,PWM4L' '2' 'G$1.RE7,PWM4H' '3' 'G$1.RC1,T2CK' '4' 'G$1.RC3,T2CK' '5' \ 'G$1.RG6,CN8,SCK2' '6' 'G$1.RG7,CN9,SD12' '7' 'G$1.RG8,CN10,SDO2' '8' 'G$1.MCLR' '9' 'G$1.RG9,CN11,SS2' '10' 'G$1.VSS1' '11' \ 'G$1.VDD1' '12' 'G$1.RE8,FLTA,INT1' '13' 'G$1.RE9,FLTB,INT2' '14' 'G$1.RB5,AN5,CN7,QEB' '15' 'G$1.RB4,AN4,CN6,QEA' '16' 'G$1.RB3,AN3,CN5,INDX' '17' \ 'G$1.RB2,AN2,CN4,LVDIN,SS1' '18' 'G$1.RB1,AN1,CN3,PGC,EMUC' '19' 'G$1.RB0,AN0,CN2,PGD,EMUD' '20' 'G$1.RB6,AN6,OCFA' '21' 'G$1.RB7,AN7' '22' 'G$1.RA9,VREF-' '23' \ 'G$1.RA10,VREF+' '24' 'G$1.AVDD' '25' 'G$1.AVSS' '26' 'G$1.RB8,AN8' '27' 'G$1.RB9,AN9' '28' 'G$1.RB10,AN10' '29' \ 'G$1.RB11,AN11' '30' 'G$1.VSS2' '31' 'G$1.VDD2' '32' 'G$1.RB12,AN12' '33' 'G$1.RB13,AN13' '34' 'G$1.RB14,AN14' '35' \ 'G$1.RB15,AN15,CN12,OCFB' '36' 'G$1.RD14,CN20,IC7' '37' 'G$1.RD15,CN21,IC8' '38' 'G$1.RF4,CN17,U2RX' '39' 'G$1.RF5,CN18,U2TX' '40' 'G$1.RF3,U1TX' '41' \ 'G$1.RF2,U1RX' '42' 'G$1.RF8,SD01,EMUD3' '43' 'G$1.RF7,SDI1' '44' 'G$1.RF6,INT0,SCK1,EMUC3' '45' 'G$1.RG3,SDA' '46' 'G$1.RG2,SCL' '47' \ 'G$1.VDD3' '48' 'G$1.OSC1,CLKI' '49' 'G$1.RC15,OSC2,CLK0' '50' 'G$1.VSS3' '51' 'G$1.RA14,INT3' '52' 'G$1.RA15,INT4' '53' \ 'G$1.RD8,IC1' '54' 'G$1.RD9,IC2' '55' 'G$1.RD10,IC3' '56' 'G$1.RD11,IC4' '57' 'G$1.RD0,OC1,EMUC2' '58' 'G$1.RC13,CN1,SOSC2,EMUD1' '59' \ 'G$1.RC14,CN0,SOSC1,T1CK,EMUC1' '60' 'G$1.RD1,OC2,EMUD2' '61' 'G$1.RD2,OC3' '62' 'G$1.RD3,OC4' '63' 'G$1.RD12,IC5' '64' 'G$1.RD13,CN19,IC6' '65' \ 'G$1.RD4,CN13,OC5' '66' 'G$1.RD5,CN14,OC6' '67' 'G$1.RD6,CN15,OC7' '68' 'G$1.RD7,CN16,OC8,UPDN' '69' 'G$1.VSS4' '70' 'G$1.VDD4' '71' \ 'G$1.RF0,C1RX' '72' 'G$1.RF1,C1TX' '73' 'G$1.RG1,C2TX' '74' 'G$1.RG0,C2RX' '75' 'G$1.RE0,PWM1L' '76' 'G$1.RE1,PWM1H' '77' \ 'G$1.RE2,PWM2L' '78' 'G$1.RE3,PWM2H' '79' 'G$1.RE4,PWM3L' '80'; Package 'TQFP-80-14' 'PF'; Technology ''; Connect 'G$1.RE5,PWM3H' '1' 'G$1.RE6,PWM4L' '2' 'G$1.RE7,PWM4H' '3' 'G$1.RC1,T2CK' '4' 'G$1.RC3,T2CK' '5' \ 'G$1.RG6,CN8,SCK2' '6' 'G$1.RG7,CN9,SD12' '7' 'G$1.RG8,CN10,SDO2' '8' 'G$1.MCLR' '9' 'G$1.RG9,CN11,SS2' '10' 'G$1.VSS1' '11' \ 'G$1.VDD1' '12' 'G$1.RE8,FLTA,INT1' '13' 'G$1.RE9,FLTB,INT2' '14' 'G$1.RB5,AN5,CN7,QEB' '15' 'G$1.RB4,AN4,CN6,QEA' '16' 'G$1.RB3,AN3,CN5,INDX' '17' \ 'G$1.RB2,AN2,CN4,LVDIN,SS1' '18' 'G$1.RB1,AN1,CN3,PGC,EMUC' '19' 'G$1.RB0,AN0,CN2,PGD,EMUD' '20' 'G$1.RB6,AN6,OCFA' '21' 'G$1.RB7,AN7' '22' 'G$1.RA9,VREF-' '23' \ 'G$1.RA10,VREF+' '24' 'G$1.AVDD' '25' 'G$1.AVSS' '26' 'G$1.RB8,AN8' '27' 'G$1.RB9,AN9' '28' 'G$1.RB10,AN10' '29' \ 'G$1.RB11,AN11' '30' 'G$1.VSS2' '31' 'G$1.VDD2' '32' 'G$1.RB12,AN12' '33' 'G$1.RB13,AN13' '34' 'G$1.RB14,AN14' '35' \ 'G$1.RB15,AN15,CN12,OCFB' '36' 'G$1.RD14,CN20,IC7' '37' 'G$1.RD15,CN21,IC8' '38' 'G$1.RF4,CN17,U2RX' '39' 'G$1.RF5,CN18,U2TX' '40' 'G$1.RF3,U1TX' '41' \ 'G$1.RF2,U1RX' '42' 'G$1.RF8,SD01,EMUD3' '43' 'G$1.RF7,SDI1' '44' 'G$1.RF6,INT0,SCK1,EMUC3' '45' 'G$1.RG3,SDA' '46' 'G$1.RG2,SCL' '47' \ 'G$1.VDD3' '48' 'G$1.OSC1,CLKI' '49' 'G$1.RC15,OSC2,CLK0' '50' 'G$1.VSS3' '51' 'G$1.RA14,INT3' '52' 'G$1.RA15,INT4' '53' \ 'G$1.RD8,IC1' '54' 'G$1.RD9,IC2' '55' 'G$1.RD10,IC3' '56' 'G$1.RD11,IC4' '57' 'G$1.RD0,OC1,EMUC2' '58' 'G$1.RC13,CN1,SOSC2,EMUD1' '59' \ 'G$1.RC14,CN0,SOSC1,T1CK,EMUC1' '60' 'G$1.RD1,OC2,EMUD2' '61' 'G$1.RD2,OC3' '62' 'G$1.RD3,OC4' '63' 'G$1.RD12,IC5' '64' 'G$1.RD13,CN19,IC6' '65' \ 'G$1.RD4,CN13,OC5' '66' 'G$1.RD5,CN14,OC6' '67' 'G$1.RD6,CN15,OC7' '68' 'G$1.RD7,CN16,OC8,UPDN' '69' 'G$1.VSS4' '70' 'G$1.VDD4' '71' \ 'G$1.RF0,C1RX' '72' 'G$1.RF1,C1TX' '73' 'G$1.RG1,C2TX' '74' 'G$1.RG0,C2RX' '75' 'G$1.RE0,PWM1L' '76' 'G$1.RE1,PWM1H' '77' \ 'G$1.RE2,PWM2L' '78' 'G$1.RE3,PWM2H' '79' 'G$1.RE4,PWM3L' '80'; Edit PIC16*F648A-?.dev; Prefix 'IC'; Description '18/20 pins, 4K prog, 256 EEPROM, 2 comp, 1 CCP, 256 RAM'; Value Off; Add 16F628 'G$1' Next 0 (0 0); Package 'DIP-18' 'P'; Technology '' 'L'; Connect 'G$1.RA2/AN2/VREF' '1' 'G$1.RA3/AN3/CMP1' '2' 'G$1.RA4/T0CKIN/CMP2' '3' 'G$1.RA5/MCLR/THV' '4' 'G$1.VSS' '5' \ 'G$1.RB0/INT' '6' 'G$1.RB1/RX/DT' '7' 'G$1.RB2/TX/CK' '8' 'G$1.RB3/CCP1' '9' 'G$1.RB4/PGM' '10' 'G$1.RB5' '11' \ 'G$1.RB6/T1OSO/T1CLK' '12' 'G$1.RB7/T1OSI' '13' 'G$1.VDD' '14' 'G$1.RA6/OSC2/CLKOUT' '15' 'G$1.RA7/OSC1/CLKIN' '16' 'G$1.RA0/AN0' '17' \ 'G$1.RA1/AN1' '18'; Edit PIC10F206-*/?.dev; Prefix 'IC'; Description '6 pins, 512 prog, 24 RAM, comparator'; Value Off; Add 10F204 'G$1' Next 0 (0 0); Package 'SOT-23' 'OT'; Technology -'' 'E' 'I'; Connect 'G$1.VDD' '5' 'G$1.VSS' '2' 'G$1.GP3/MCLR' '6' 'G$1.GP2/COUT/T0CKI/FOSC4' '4' 'G$1.GP0/CIN+/PGD' '1' \ 'G$1.GP1/CIN-/PGC' '3'; Edit PIC30F4011-?.dev; Prefix 'IC'; Description 'dsPIC, 40/44 pin, 16Kw prog, 2Kb RAM, 1Kb EEPROM, 9 A/D, 2 MPWM, 2 UART'; Value Off; Add 30F4011 'G$1' Next 0 (0 0); Package 'TQFP-44-10' 'PT'; Technology ''; Connect 'G$1.RF2,U1RX,SDA,SDI1,PGC,EMUC' '1' 'G$1.RF5,U2TX,CN18' '2' 'G$1.RF4,U2RX,CN17' '3' 'G$1.RF1,CTX1' '4' 'G$1.RF0,CRX1' '5' \ 'G$1.VSS1' '6' 'G$1.VDD1' '7' 'G$1.RE5,PWM3H' '8' 'G$1.RE4,PWM3L' '9' 'G$1.RE3,PWM2H' '10' 'G$1.RE2,PWM2L' '11' \ 'G$1.RE1,PWM1H' '14' 'G$1.RE0,PWM1L' '15' 'G$1.AVSS' '16' 'G$1.AVDD' '17' 'G$1.MCLR' '18' 'G$1.RB0,AN0,VREF+,CN2,EMUD3' '19' \ 'G$1.RB1,AN1,VREF-,CN3,EMUC3' '20' 'G$1.RB2,AN2,CN4,SS1' '21' 'G$1.RB3,AN3,CN5,INDX' '22' 'G$1.RB4,AN4,CN6,IC7,QEA' '23' 'G$1.RB5,AN5,CN7,IC8,QEB' '24' 'G$1.RB6,AN6,OCFA' '25' \ 'G$1.RB7,AN7' '26' 'G$1.RB8,AN8' '27' 'G$1.VDD2' '28' 'G$1.VSS2' '29' 'G$1.OSC1,CLKIN' '30' 'G$1.RC15,OSC2,CLKO' '31' \ 'G$1.RC13,CN1,U1ATX,T2CK,SOSCI,EMUD1' '32' 'G$1.RC14,CN0,U1ARX,T1CK,SOSCO,EMUC1' '35' 'G$1.RE8,INT0,FLTA' '36' 'G$1.RD1,INT2,IC2,OC2,EMUD2' '37' 'G$1.RD3,OC4' '38' 'G$1.VSS3' '39' \ 'G$1.VDD3' '40' 'G$1.RD2,OC3' '41' 'G$1.RD0,INT1,IC1,OC1,EMUC2' '42' 'G$1.RF6,SCK1' '43' 'G$1.RF3,U1TX,SCL,SDO1,PGD,EMUD' '44'; Edit PIC10F204-*/?.dev; Prefix 'IC'; Description '6 pins, 256 prog, 16 RAM, comparator'; Value Off; Add 10F204 'G$1' Next 0 (0 0); Package 'SOT-23' 'OT'; Technology -'' 'E' 'I'; Connect 'G$1.VDD' '5' 'G$1.VSS' '2' 'G$1.GP3/MCLR' '6' 'G$1.GP2/COUT/T0CKI/FOSC4' '4' 'G$1.GP0/CIN+/PGD' '1' \ 'G$1.GP1/CIN-/PGC' '3'; Edit PIC10F200-*/?.dev; Prefix 'IC'; Description '6 pins, 256 prog, 16 RAM'; Value Off; Add 10F200 'G$1' Next 0 (0 0); Package 'SOT-23' 'OT'; Technology -'' 'E' 'I'; Connect 'G$1.VDD' '5' 'G$1.VSS' '2' 'G$1.GP3/MCLR' '6' 'G$1.GP2/T0CKI/FOSC4' '4' 'G$1.GP0/PGD' '1' \ 'G$1.GP1/PGC' '3'; Edit PIC10F202-*/?.dev; Prefix 'IC'; Description '6 pins, 512 prog, 24 RAM'; Value Off; Add 10F200 'G$1' Next 0 (0 0); Package 'SOT-23' 'OT'; Technology -'' 'E' 'I'; Connect 'G$1.VDD' '5' 'G$1.VSS' '2' 'G$1.GP3/MCLR' '6' 'G$1.GP2/T0CKI/FOSC4' '4' 'G$1.GP0/PGD' '1' \ 'G$1.GP1/PGC' '3'; Edit PIC30F4012-*/?.dev; Prefix 'IC'; Description 'dsPIC, 28 pin, 16Kw prog, 2Kb RAM, 1Kb EEPROM, 6 A/D, 2 MPWM, 1 UART'; Value Off; Add 30F4012 'G$1' Next 0 (0 0); Package 'SOIC-28' 'SO'; Technology -'' '20E' '20I' '30E' '30I'; Connect 'G$1.MCLR' '1' 'G$1.RB0,CN2' '2' 'G$1.RB1,CN3' '3' 'G$1.RB2,CN4' '4' 'G$1.RB3,CN5' '5' \ 'G$1.RB4,CN6' '6' 'G$1.RB5,CN7' '7' 'G$1.VSS1' '8' 'G$1.OSC1,CLKI' '9' 'G$1.RC15,OSC2,CLKO' '10' 'G$1.RC13,CN1' '11' \ 'G$1.RC14,CN0' '12' 'G$1.VDD1' '13' 'G$1.RD1,INT2' '14' 'G$1.RD0,INT1' '15' 'G$1.RE8,INT0' '16' 'G$1.RF3,PGD,EMUD' '17' \ 'G$1.RF2,PGC,EMUC' '18' 'G$1.VSS2' '19' 'G$1.VDD2' '20' 'G$1.PWM3H,RE5' '21' 'G$1.PWM3L,RE4' '22' 'G$1.PWM2H,RE3' '23' \ 'G$1.PWM2L,RE2' '24' 'G$1.PWM1H,RE1' '25' 'G$1.PWM1L,RE0' '26' 'G$1.AVSS' '27' 'G$1.AVDD' '28'; Package 'PDIP-28' 'SP'; Technology -'' '20E' '20I' '30E' '30I'; Connect 'G$1.MCLR' '1' 'G$1.RB0,CN2' '2' 'G$1.RB1,CN3' '3' 'G$1.RB2,CN4' '4' 'G$1.RB3,CN5' '5' \ 'G$1.RB4,CN6' '6' 'G$1.RB5,CN7' '7' 'G$1.VSS1' '8' 'G$1.OSC1,CLKI' '9' 'G$1.RC15,OSC2,CLKO' '10' 'G$1.RC13,CN1' '11' \ 'G$1.RC14,CN0' '12' 'G$1.VDD1' '13' 'G$1.RD1,INT2' '14' 'G$1.RD0,INT1' '15' 'G$1.RE8,INT0' '16' 'G$1.RF3,PGD,EMUD' '17' \ 'G$1.RF2,PGC,EMUC' '18' 'G$1.VSS2' '19' 'G$1.VDD2' '20' 'G$1.PWM3H,RE5' '21' 'G$1.PWM3L,RE4' '22' 'G$1.PWM2H,RE3' '23' \ 'G$1.PWM2L,RE2' '24' 'G$1.PWM1H,RE1' '25' 'G$1.PWM1L,RE0' '26' 'G$1.AVSS' '27' 'G$1.AVDD' '28'; Grid inch;